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[u-boot] / arch / arm / dts / uniphier-proxstream2.dtsi
1 /*
2  * Device Tree Source for UniPhier ProXstream2 SoC
3  *
4  * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
5  *
6  * SPDX-License-Identifier:     GPL-2.0+        X11
7  */
8
9 /include/ "uniphier-common32.dtsi"
10
11 / {
12         compatible = "socionext,proxstream2";
13
14         cpus {
15                 #address-cells = <1>;
16                 #size-cells = <0>;
17                 enable-method = "socionext,uniphier-smp";
18
19                 cpu@0 {
20                         device_type = "cpu";
21                         compatible = "arm,cortex-a9";
22                         reg = <0>;
23                         next-level-cache = <&l2>;
24                 };
25
26                 cpu@1 {
27                         device_type = "cpu";
28                         compatible = "arm,cortex-a9";
29                         reg = <1>;
30                         next-level-cache = <&l2>;
31                 };
32
33                 cpu@2 {
34                         device_type = "cpu";
35                         compatible = "arm,cortex-a9";
36                         reg = <2>;
37                         next-level-cache = <&l2>;
38                 };
39
40                 cpu@3 {
41                         device_type = "cpu";
42                         compatible = "arm,cortex-a9";
43                         reg = <3>;
44                         next-level-cache = <&l2>;
45                 };
46         };
47
48         clocks {
49                 arm_timer_clk: arm_timer_clk {
50                         #clock-cells = <0>;
51                         compatible = "fixed-clock";
52                         clock-frequency = <50000000>;
53                 };
54
55                 uart_clk: uart_clk {
56                         #clock-cells = <0>;
57                         compatible = "fixed-clock";
58                         clock-frequency = <88900000>;
59                 };
60
61                 i2c_clk: i2c_clk {
62                         #clock-cells = <0>;
63                         compatible = "fixed-clock";
64                         clock-frequency = <50000000>;
65                 };
66         };
67 };
68
69 &soc {
70         l2: l2-cache@500c0000 {
71                 compatible = "socionext,uniphier-system-cache";
72                 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>;
73                 interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>;
74                 cache-unified;
75                 cache-size = <(1280 * 1024)>;
76                 cache-sets = <512>;
77                 cache-line-size = <128>;
78                 cache-level = <2>;
79         };
80
81         port0x: gpio@55000008 {
82                 compatible = "socionext,uniphier-gpio";
83                 reg = <0x55000008 0x8>;
84                 gpio-controller;
85                 #gpio-cells = <2>;
86         };
87
88         port1x: gpio@55000010 {
89                 compatible = "socionext,uniphier-gpio";
90                 reg = <0x55000010 0x8>;
91                 gpio-controller;
92                 #gpio-cells = <2>;
93         };
94
95         port2x: gpio@55000018 {
96                 compatible = "socionext,uniphier-gpio";
97                 reg = <0x55000018 0x8>;
98                 gpio-controller;
99                 #gpio-cells = <2>;
100         };
101
102         port3x: gpio@55000020 {
103                 compatible = "socionext,uniphier-gpio";
104                 reg = <0x55000020 0x8>;
105                 gpio-controller;
106                 #gpio-cells = <2>;
107         };
108
109         port4: gpio@55000028 {
110                 compatible = "socionext,uniphier-gpio";
111                 reg = <0x55000028 0x8>;
112                 gpio-controller;
113                 #gpio-cells = <2>;
114         };
115
116         port5x: gpio@55000030 {
117                 compatible = "socionext,uniphier-gpio";
118                 reg = <0x55000030 0x8>;
119                 gpio-controller;
120                 #gpio-cells = <2>;
121         };
122
123         port6x: gpio@55000038 {
124                 compatible = "socionext,uniphier-gpio";
125                 reg = <0x55000038 0x8>;
126                 gpio-controller;
127                 #gpio-cells = <2>;
128         };
129
130         port7x: gpio@55000040 {
131                 compatible = "socionext,uniphier-gpio";
132                 reg = <0x55000040 0x8>;
133                 gpio-controller;
134                 #gpio-cells = <2>;
135         };
136
137         port8x: gpio@55000048 {
138                 compatible = "socionext,uniphier-gpio";
139                 reg = <0x55000048 0x8>;
140                 gpio-controller;
141                 #gpio-cells = <2>;
142         };
143
144         port9x: gpio@55000050 {
145                 compatible = "socionext,uniphier-gpio";
146                 reg = <0x55000050 0x8>;
147                 gpio-controller;
148                 #gpio-cells = <2>;
149         };
150
151         port10x: gpio@55000058 {
152                 compatible = "socionext,uniphier-gpio";
153                 reg = <0x55000058 0x8>;
154                 gpio-controller;
155                 #gpio-cells = <2>;
156         };
157
158         port12x: gpio@55000068 {
159                 compatible = "socionext,uniphier-gpio";
160                 reg = <0x55000068 0x8>;
161                 gpio-controller;
162                 #gpio-cells = <2>;
163         };
164
165         port13x: gpio@55000070 {
166                 compatible = "socionext,uniphier-gpio";
167                 reg = <0x55000070 0x8>;
168                 gpio-controller;
169                 #gpio-cells = <2>;
170         };
171
172         port14x: gpio@55000078 {
173                 compatible = "socionext,uniphier-gpio";
174                 reg = <0x55000078 0x8>;
175                 gpio-controller;
176                 #gpio-cells = <2>;
177         };
178
179         port15x: gpio@55000080 {
180                 compatible = "socionext,uniphier-gpio";
181                 reg = <0x55000080 0x8>;
182                 gpio-controller;
183                 #gpio-cells = <2>;
184         };
185
186         port16x: gpio@55000088 {
187                 compatible = "socionext,uniphier-gpio";
188                 reg = <0x55000088 0x8>;
189                 gpio-controller;
190                 #gpio-cells = <2>;
191         };
192
193         port17x: gpio@550000a0 {
194                 compatible = "socionext,uniphier-gpio";
195                 reg = <0x550000a0 0x8>;
196                 gpio-controller;
197                 #gpio-cells = <2>;
198         };
199
200         port18x: gpio@550000a8 {
201                 compatible = "socionext,uniphier-gpio";
202                 reg = <0x550000a8 0x8>;
203                 gpio-controller;
204                 #gpio-cells = <2>;
205         };
206
207         port19x: gpio@550000b0 {
208                 compatible = "socionext,uniphier-gpio";
209                 reg = <0x550000b0 0x8>;
210                 gpio-controller;
211                 #gpio-cells = <2>;
212         };
213
214         port20x: gpio@550000b8 {
215                 compatible = "socionext,uniphier-gpio";
216                 reg = <0x550000b8 0x8>;
217                 gpio-controller;
218                 #gpio-cells = <2>;
219         };
220
221         port21x: gpio@550000c0 {
222                 compatible = "socionext,uniphier-gpio";
223                 reg = <0x550000c0 0x8>;
224                 gpio-controller;
225                 #gpio-cells = <2>;
226         };
227
228         port22x: gpio@550000c8 {
229                 compatible = "socionext,uniphier-gpio";
230                 reg = <0x550000c8 0x8>;
231                 gpio-controller;
232                 #gpio-cells = <2>;
233         };
234
235         port23x: gpio@550000d0 {
236                 compatible = "socionext,uniphier-gpio";
237                 reg = <0x550000d0 0x8>;
238                 gpio-controller;
239                 #gpio-cells = <2>;
240         };
241
242         port24x: gpio@550000d8 {
243                 compatible = "socionext,uniphier-gpio";
244                 reg = <0x550000d8 0x8>;
245                 gpio-controller;
246                 #gpio-cells = <2>;
247         };
248
249         port25x: gpio@550000e0 {
250                 compatible = "socionext,uniphier-gpio";
251                 reg = <0x550000e0 0x8>;
252                 gpio-controller;
253                 #gpio-cells = <2>;
254         };
255
256         port26x: gpio@550000e8 {
257                 compatible = "socionext,uniphier-gpio";
258                 reg = <0x550000e8 0x8>;
259                 gpio-controller;
260                 #gpio-cells = <2>;
261         };
262
263         port27x: gpio@550000f0 {
264                 compatible = "socionext,uniphier-gpio";
265                 reg = <0x550000f0 0x8>;
266                 gpio-controller;
267                 #gpio-cells = <2>;
268         };
269
270         port28x: gpio@550000f8 {
271                 compatible = "socionext,uniphier-gpio";
272                 reg = <0x550000f8 0x8>;
273                 gpio-controller;
274                 #gpio-cells = <2>;
275         };
276
277         i2c0: i2c@58780000 {
278                 compatible = "socionext,uniphier-fi2c";
279                 status = "disabled";
280                 reg = <0x58780000 0x80>;
281                 #address-cells = <1>;
282                 #size-cells = <0>;
283                 interrupts = <0 41 4>;
284                 pinctrl-names = "default";
285                 pinctrl-0 = <&pinctrl_i2c0>;
286                 clocks = <&i2c_clk>;
287                 clock-frequency = <100000>;
288         };
289
290         i2c1: i2c@58781000 {
291                 compatible = "socionext,uniphier-fi2c";
292                 status = "disabled";
293                 reg = <0x58781000 0x80>;
294                 #address-cells = <1>;
295                 #size-cells = <0>;
296                 interrupts = <0 42 4>;
297                 pinctrl-names = "default";
298                 pinctrl-0 = <&pinctrl_i2c1>;
299                 clocks = <&i2c_clk>;
300                 clock-frequency = <100000>;
301         };
302
303         i2c2: i2c@58782000 {
304                 compatible = "socionext,uniphier-fi2c";
305                 status = "disabled";
306                 reg = <0x58782000 0x80>;
307                 #address-cells = <1>;
308                 #size-cells = <0>;
309                 pinctrl-names = "default";
310                 pinctrl-0 = <&pinctrl_i2c2>;
311                 interrupts = <0 43 4>;
312                 clocks = <&i2c_clk>;
313                 clock-frequency = <100000>;
314         };
315
316         i2c3: i2c@58783000 {
317                 compatible = "socionext,uniphier-fi2c";
318                 status = "disabled";
319                 reg = <0x58783000 0x80>;
320                 #address-cells = <1>;
321                 #size-cells = <0>;
322                 interrupts = <0 44 4>;
323                 pinctrl-names = "default";
324                 pinctrl-0 = <&pinctrl_i2c3>;
325                 clocks = <&i2c_clk>;
326                 clock-frequency = <100000>;
327         };
328
329         /* chip-internal connection for DMD */
330         i2c4: i2c@58784000 {
331                 compatible = "socionext,uniphier-fi2c";
332                 reg = <0x58784000 0x80>;
333                 #address-cells = <1>;
334                 #size-cells = <0>;
335                 interrupts = <0 45 4>;
336                 clocks = <&i2c_clk>;
337                 clock-frequency = <400000>;
338         };
339
340         /* chip-internal connection for STM */
341         i2c5: i2c@58785000 {
342                 compatible = "socionext,uniphier-fi2c";
343                 reg = <0x58785000 0x80>;
344                 #address-cells = <1>;
345                 #size-cells = <0>;
346                 interrupts = <0 25 4>;
347                 clocks = <&i2c_clk>;
348                 clock-frequency = <400000>;
349         };
350
351         /* chip-internal connection for HDMI */
352         i2c6: i2c@58786000 {
353                 compatible = "socionext,uniphier-fi2c";
354                 reg = <0x58786000 0x80>;
355                 #address-cells = <1>;
356                 #size-cells = <0>;
357                 interrupts = <0 26 4>;
358                 clocks = <&i2c_clk>;
359                 clock-frequency = <400000>;
360         };
361
362         emmc: sdhc@5a000000 {
363                 compatible = "socionext,uniphier-sdhc";
364                 status = "disabled";
365                 reg = <0x5a000000 0x800>;
366                 interrupts = <0 78 4>;
367                 pinctrl-names = "default";
368                 pinctrl-0 = <&pinctrl_emmc>;
369                 clocks = <&mio 1>;
370                 bus-width = <8>;
371                 non-removable;
372         };
373
374         sd: sdhc@5a400000 {
375                 compatible = "socionext,uniphier-sdhc";
376                 status = "disabled";
377                 reg = <0x5a400000 0x800>;
378                 interrupts = <0 76 4>;
379                 pinctrl-names = "default", "1.8v";
380                 pinctrl-0 = <&pinctrl_sd>;
381                 pinctrl-1 = <&pinctrl_sd_1v8>;
382                 clocks = <&mio 0>;
383                 bus-width = <4>;
384         };
385
386         usb0: usb@65a00000 {
387                 compatible = "socionext,uniphier-xhci", "generic-xhci";
388                 status = "disabled";
389                 reg = <0x65a00000 0x100>;
390                 interrupts = <0 134 4>;
391                 pinctrl-names = "default";
392                 pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
393         };
394
395         usb1: usb@65c00000 {
396                 compatible = "socionext,uniphier-xhci", "generic-xhci";
397                 status = "disabled";
398                 reg = <0x65c00000 0x100>;
399                 interrupts = <0 137 4>;
400                 pinctrl-names = "default";
401                 pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
402         };
403 };
404
405 &refclk {
406         clock-frequency = <25000000>;
407 };
408
409 &serial0 {
410         clock-frequency = <88900000>;
411 };
412
413 &serial1 {
414         clock-frequency = <88900000>;
415 };
416
417 &serial2 {
418         clock-frequency = <88900000>;
419 };
420
421 &serial3 {
422         clock-frequency = <88900000>;
423 };
424
425 &mio {
426         compatible = "socionext,proxstream2-mioctrl";
427         clock-names = "stdmac";
428         clocks = <&sysctrl 10>;
429 };
430
431 &peri {
432         compatible = "socionext,proxstream2-perictrl";
433         clock-names = "uart", "fi2c";
434         clocks = <&sysctrl 3>, <&sysctrl 4>;
435 };
436
437 &pinctrl {
438         compatible = "socionext,proxstream2-pinctrl", "syscon";
439 };
440
441 &sysctrl {
442         compatible = "socionext,proxstream2-sysctrl";
443 };