git.sur5r.net Git - u-boot/blob - arch/arm/dts/uniphier-pxs2.dtsi

   1 /*
   2  * Device Tree Source for UniPhier PXs2 SoC
   3  *
   4  * Copyright (C) 2015-2016 Socionext Inc.
   5  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
   6  *
   7  * This file is dual-licensed: you can use it either under the terms
   8  * of the GPL or the X11 license, at your option. Note that this dual
   9  * licensing only applies to this file, and not this project as a
  10  * whole.
  11  *
  12  *  a) This file is free software; you can redistribute it and/or
  13  *     modify it under the terms of the GNU General Public License as
  14  *     published by the Free Software Foundation; either version 2 of the
  15  *     License, or (at your option) any later version.
  16  *
  17  *     This file is distributed in the hope that it will be useful,
  18  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  *     GNU General Public License for more details.
  21  *
  22  * Or, alternatively,
  23  *
  24  *  b) Permission is hereby granted, free of charge, to any person
  25  *     obtaining a copy of this software and associated documentation
  26  *     files (the "Software"), to deal in the Software without
  27  *     restriction, including without limitation the rights to use,
  28  *     copy, modify, merge, publish, distribute, sublicense, and/or
  29  *     sell copies of the Software, and to permit persons to whom the
  30  *     Software is furnished to do so, subject to the following
  31  *     conditions:
  32  *
  33  *     The above copyright notice and this permission notice shall be
  34  *     included in all copies or substantial portions of the Software.
  35  *
  36  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  37  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  38  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  39  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  40  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  41  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  42  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  43  *     OTHER DEALINGS IN THE SOFTWARE.
  44  */
  45
  46 / {
  47         compatible = "socionext,uniphier-pxs2";
  48         #address-cells = <1>;
  49         #size-cells = <1>;
  50
  51         cpus {
  52                 #address-cells = <1>;
  53                 #size-cells = <0>;
  54
  55                 cpu@0 {
  56                         device_type = "cpu";
  57                         compatible = "arm,cortex-a9";
  58                         reg = <0>;
  59                         clocks = <&sys_clk 32>;
  60                         enable-method = "psci";
  61                         next-level-cache = <&l2>;
  62                         operating-points-v2 = <&cpu_opp>;
  63                 };
  64
  65                 cpu@1 {
  66                         device_type = "cpu";
  67                         compatible = "arm,cortex-a9";
  68                         reg = <1>;
  69                         clocks = <&sys_clk 32>;
  70                         enable-method = "psci";
  71                         next-level-cache = <&l2>;
  72                         operating-points-v2 = <&cpu_opp>;
  73                 };
  74
  75                 cpu@2 {
  76                         device_type = "cpu";
  77                         compatible = "arm,cortex-a9";
  78                         reg = <2>;
  79                         clocks = <&sys_clk 32>;
  80                         enable-method = "psci";
  81                         next-level-cache = <&l2>;
  82                         operating-points-v2 = <&cpu_opp>;
  83                 };
  84
  85                 cpu@3 {
  86                         device_type = "cpu";
  87                         compatible = "arm,cortex-a9";
  88                         reg = <3>;
  89                         clocks = <&sys_clk 32>;
  90                         enable-method = "psci";
  91                         next-level-cache = <&l2>;
  92                         operating-points-v2 = <&cpu_opp>;
  93                 };
  94         };
  95
  96         cpu_opp: opp_table {
  97                 compatible = "operating-points-v2";
  98                 opp-shared;
  99
 100                 opp-100000000 {
 101                         opp-hz = /bits/ 64 <100000000>;
 102                         clock-latency-ns = <300>;
 103                 };
 104                 opp-150000000 {
 105                         opp-hz = /bits/ 64 <150000000>;
 106                         clock-latency-ns = <300>;
 107                 };
 108                 opp-200000000 {
 109                         opp-hz = /bits/ 64 <200000000>;
 110                         clock-latency-ns = <300>;
 111                 };
 112                 opp-300000000 {
 113                         opp-hz = /bits/ 64 <300000000>;
 114                         clock-latency-ns = <300>;
 115                 };
 116                 opp-400000000 {
 117                         opp-hz = /bits/ 64 <400000000>;
 118                         clock-latency-ns = <300>;
 119                 };
 120                 opp-600000000 {
 121                         opp-hz = /bits/ 64 <600000000>;
 122                         clock-latency-ns = <300>;
 123                 };
 124                 opp-800000000 {
 125                         opp-hz = /bits/ 64 <800000000>;
 126                         clock-latency-ns = <300>;
 127                 };
 128                 opp-1200000000 {
 129                         opp-hz = /bits/ 64 <1200000000>;
 130                         clock-latency-ns = <300>;
 131                 };
 132         };
 133
 134         psci {
 135                 compatible = "arm,psci-0.2";
 136                 method = "smc";
 137         };
 138
 139         clocks {
 140                 refclk: ref {
 141                         compatible = "fixed-clock";
 142                         #clock-cells = <0>;
 143                         clock-frequency = <25000000>;
 144                 };
 145
 146                 arm_timer_clk: arm_timer_clk {
 147                         #clock-cells = <0>;
 148                         compatible = "fixed-clock";
 149                         clock-frequency = <50000000>;
 150                 };
 151         };
 152
 153         soc {
 154                 compatible = "simple-bus";
 155                 #address-cells = <1>;
 156                 #size-cells = <1>;
 157                 ranges;
 158                 interrupt-parent = <&intc>;
 159                 u-boot,dm-pre-reloc;
 160
 161                 l2: l2-cache@500c0000 {
 162                         compatible = "socionext,uniphier-system-cache";
 163                         reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
 164                               <0x506c0000 0x400>;
 165                         interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>;
 166                         cache-unified;
 167                         cache-size = <(1280 * 1024)>;
 168                         cache-sets = <512>;
 169                         cache-line-size = <128>;
 170                         cache-level = <2>;
 171                 };
 172
 173                 serial0: serial@54006800 {
 174                         compatible = "socionext,uniphier-uart";
 175                         status = "disabled";
 176                         reg = <0x54006800 0x40>;
 177                         interrupts = <0 33 4>;
 178                         pinctrl-names = "default";
 179                         pinctrl-0 = <&pinctrl_uart0>;
 180                         clocks = <&peri_clk 0>;
 181                         clock-frequency = <88900000>;
 182                 };
 183
 184                 serial1: serial@54006900 {
 185                         compatible = "socionext,uniphier-uart";
 186                         status = "disabled";
 187                         reg = <0x54006900 0x40>;
 188                         interrupts = <0 35 4>;
 189                         pinctrl-names = "default";
 190                         pinctrl-0 = <&pinctrl_uart1>;
 191                         clocks = <&peri_clk 1>;
 192                         clock-frequency = <88900000>;
 193                 };
 194
 195                 serial2: serial@54006a00 {
 196                         compatible = "socionext,uniphier-uart";
 197                         status = "disabled";
 198                         reg = <0x54006a00 0x40>;
 199                         interrupts = <0 37 4>;
 200                         pinctrl-names = "default";
 201                         pinctrl-0 = <&pinctrl_uart2>;
 202                         clocks = <&peri_clk 2>;
 203                         clock-frequency = <88900000>;
 204                 };
 205
 206                 serial3: serial@54006b00 {
 207                         compatible = "socionext,uniphier-uart";
 208                         status = "disabled";
 209                         reg = <0x54006b00 0x40>;
 210                         interrupts = <0 177 4>;
 211                         pinctrl-names = "default";
 212                         pinctrl-0 = <&pinctrl_uart3>;
 213                         clocks = <&peri_clk 3>;
 214                         clock-frequency = <88900000>;
 215                 };
 216
 217                 port0x: gpio@55000008 {
 218                         compatible = "socionext,uniphier-gpio";
 219                         reg = <0x55000008 0x8>;
 220                         gpio-controller;
 221                         #gpio-cells = <2>;
 222                 };
 223
 224                 port1x: gpio@55000010 {
 225                         compatible = "socionext,uniphier-gpio";
 226                         reg = <0x55000010 0x8>;
 227                         gpio-controller;
 228                         #gpio-cells = <2>;
 229                 };
 230
 231                 port2x: gpio@55000018 {
 232                         compatible = "socionext,uniphier-gpio";
 233                         reg = <0x55000018 0x8>;
 234                         gpio-controller;
 235                         #gpio-cells = <2>;
 236                 };
 237
 238                 port3x: gpio@55000020 {
 239                         compatible = "socionext,uniphier-gpio";
 240                         reg = <0x55000020 0x8>;
 241                         gpio-controller;
 242                         #gpio-cells = <2>;
 243                 };
 244
 245                 port4: gpio@55000028 {
 246                         compatible = "socionext,uniphier-gpio";
 247                         reg = <0x55000028 0x8>;
 248                         gpio-controller;
 249                         #gpio-cells = <2>;
 250                 };
 251
 252                 port5x: gpio@55000030 {
 253                         compatible = "socionext,uniphier-gpio";
 254                         reg = <0x55000030 0x8>;
 255                         gpio-controller;
 256                         #gpio-cells = <2>;
 257                 };
 258
 259                 port6x: gpio@55000038 {
 260                         compatible = "socionext,uniphier-gpio";
 261                         reg = <0x55000038 0x8>;
 262                         gpio-controller;
 263                         #gpio-cells = <2>;
 264                 };
 265
 266                 port7x: gpio@55000040 {
 267                         compatible = "socionext,uniphier-gpio";
 268                         reg = <0x55000040 0x8>;
 269                         gpio-controller;
 270                         #gpio-cells = <2>;
 271                 };
 272
 273                 port8x: gpio@55000048 {
 274                         compatible = "socionext,uniphier-gpio";
 275                         reg = <0x55000048 0x8>;
 276                         gpio-controller;
 277                         #gpio-cells = <2>;
 278                 };
 279
 280                 port9x: gpio@55000050 {
 281                         compatible = "socionext,uniphier-gpio";
 282                         reg = <0x55000050 0x8>;
 283                         gpio-controller;
 284                         #gpio-cells = <2>;
 285                 };
 286
 287                 port10x: gpio@55000058 {
 288                         compatible = "socionext,uniphier-gpio";
 289                         reg = <0x55000058 0x8>;
 290                         gpio-controller;
 291                         #gpio-cells = <2>;
 292                 };
 293
 294                 port12x: gpio@55000068 {
 295                         compatible = "socionext,uniphier-gpio";
 296                         reg = <0x55000068 0x8>;
 297                         gpio-controller;
 298                         #gpio-cells = <2>;
 299                 };
 300
 301                 port13x: gpio@55000070 {
 302                         compatible = "socionext,uniphier-gpio";
 303                         reg = <0x55000070 0x8>;
 304                         gpio-controller;
 305                         #gpio-cells = <2>;
 306                 };
 307
 308                 port14x: gpio@55000078 {
 309                         compatible = "socionext,uniphier-gpio";
 310                         reg = <0x55000078 0x8>;
 311                         gpio-controller;
 312                         #gpio-cells = <2>;
 313                 };
 314
 315                 port15x: gpio@55000080 {
 316                         compatible = "socionext,uniphier-gpio";
 317                         reg = <0x55000080 0x8>;
 318                         gpio-controller;
 319                         #gpio-cells = <2>;
 320                 };
 321
 322                 port16x: gpio@55000088 {
 323                         compatible = "socionext,uniphier-gpio";
 324                         reg = <0x55000088 0x8>;
 325                         gpio-controller;
 326                         #gpio-cells = <2>;
 327                 };
 328
 329                 port17x: gpio@550000a0 {
 330                         compatible = "socionext,uniphier-gpio";
 331                         reg = <0x550000a0 0x8>;
 332                         gpio-controller;
 333                         #gpio-cells = <2>;
 334                 };
 335
 336                 port18x: gpio@550000a8 {
 337                         compatible = "socionext,uniphier-gpio";
 338                         reg = <0x550000a8 0x8>;
 339                         gpio-controller;
 340                         #gpio-cells = <2>;
 341                 };
 342
 343                 port19x: gpio@550000b0 {
 344                         compatible = "socionext,uniphier-gpio";
 345                         reg = <0x550000b0 0x8>;
 346                         gpio-controller;
 347                         #gpio-cells = <2>;
 348                 };
 349
 350                 port20x: gpio@550000b8 {
 351                         compatible = "socionext,uniphier-gpio";
 352                         reg = <0x550000b8 0x8>;
 353                         gpio-controller;
 354                         #gpio-cells = <2>;
 355                 };
 356
 357                 port21x: gpio@550000c0 {
 358                         compatible = "socionext,uniphier-gpio";
 359                         reg = <0x550000c0 0x8>;
 360                         gpio-controller;
 361                         #gpio-cells = <2>;
 362                 };
 363
 364                 port22x: gpio@550000c8 {
 365                         compatible = "socionext,uniphier-gpio";
 366                         reg = <0x550000c8 0x8>;
 367                         gpio-controller;
 368                         #gpio-cells = <2>;
 369                 };
 370
 371                 port23x: gpio@550000d0 {
 372                         compatible = "socionext,uniphier-gpio";
 373                         reg = <0x550000d0 0x8>;
 374                         gpio-controller;
 375                         #gpio-cells = <2>;
 376                 };
 377
 378                 port24x: gpio@550000d8 {
 379                         compatible = "socionext,uniphier-gpio";
 380                         reg = <0x550000d8 0x8>;
 381                         gpio-controller;
 382                         #gpio-cells = <2>;
 383                 };
 384
 385                 port25x: gpio@550000e0 {
 386                         compatible = "socionext,uniphier-gpio";
 387                         reg = <0x550000e0 0x8>;
 388                         gpio-controller;
 389                         #gpio-cells = <2>;
 390                 };
 391
 392                 port26x: gpio@550000e8 {
 393                         compatible = "socionext,uniphier-gpio";
 394                         reg = <0x550000e8 0x8>;
 395                         gpio-controller;
 396                         #gpio-cells = <2>;
 397                 };
 398
 399                 port27x: gpio@550000f0 {
 400                         compatible = "socionext,uniphier-gpio";
 401                         reg = <0x550000f0 0x8>;
 402                         gpio-controller;
 403                         #gpio-cells = <2>;
 404                 };
 405
 406                 port28x: gpio@550000f8 {
 407                         compatible = "socionext,uniphier-gpio";
 408                         reg = <0x550000f8 0x8>;
 409                         gpio-controller;
 410                         #gpio-cells = <2>;
 411                 };
 412
 413                 i2c0: i2c@58780000 {
 414                         compatible = "socionext,uniphier-fi2c";
 415                         status = "disabled";
 416                         reg = <0x58780000 0x80>;
 417                         #address-cells = <1>;
 418                         #size-cells = <0>;
 419                         interrupts = <0 41 4>;
 420                         pinctrl-names = "default";
 421                         pinctrl-0 = <&pinctrl_i2c0>;
 422                         clocks = <&peri_clk 4>;
 423                         clock-frequency = <100000>;
 424                 };
 425
 426                 i2c1: i2c@58781000 {
 427                         compatible = "socionext,uniphier-fi2c";
 428                         status = "disabled";
 429                         reg = <0x58781000 0x80>;
 430                         #address-cells = <1>;
 431                         #size-cells = <0>;
 432                         interrupts = <0 42 4>;
 433                         pinctrl-names = "default";
 434                         pinctrl-0 = <&pinctrl_i2c1>;
 435                         clocks = <&peri_clk 5>;
 436                         clock-frequency = <100000>;
 437                 };
 438
 439                 i2c2: i2c@58782000 {
 440                         compatible = "socionext,uniphier-fi2c";
 441                         status = "disabled";
 442                         reg = <0x58782000 0x80>;
 443                         #address-cells = <1>;
 444                         #size-cells = <0>;
 445                         interrupts = <0 43 4>;
 446                         pinctrl-names = "default";
 447                         pinctrl-0 = <&pinctrl_i2c2>;
 448                         clocks = <&peri_clk 6>;
 449                         clock-frequency = <100000>;
 450                 };
 451
 452                 i2c3: i2c@58783000 {
 453                         compatible = "socionext,uniphier-fi2c";
 454                         status = "disabled";
 455                         reg = <0x58783000 0x80>;
 456                         #address-cells = <1>;
 457                         #size-cells = <0>;
 458                         interrupts = <0 44 4>;
 459                         pinctrl-names = "default";
 460                         pinctrl-0 = <&pinctrl_i2c3>;
 461                         clocks = <&peri_clk 7>;
 462                         clock-frequency = <100000>;
 463                 };
 464
 465                 /* chip-internal connection for DMD */
 466                 i2c4: i2c@58784000 {
 467                         compatible = "socionext,uniphier-fi2c";
 468                         reg = <0x58784000 0x80>;
 469                         #address-cells = <1>;
 470                         #size-cells = <0>;
 471                         interrupts = <0 45 4>;
 472                         clocks = <&peri_clk 8>;
 473                         clock-frequency = <400000>;
 474                 };
 475
 476                 /* chip-internal connection for STM */
 477                 i2c5: i2c@58785000 {
 478                         compatible = "socionext,uniphier-fi2c";
 479                         reg = <0x58785000 0x80>;
 480                         #address-cells = <1>;
 481                         #size-cells = <0>;
 482                         interrupts = <0 25 4>;
 483                         clocks = <&peri_clk 9>;
 484                         clock-frequency = <400000>;
 485                 };
 486
 487                 /* chip-internal connection for HDMI */
 488                 i2c6: i2c@58786000 {
 489                         compatible = "socionext,uniphier-fi2c";
 490                         reg = <0x58786000 0x80>;
 491                         #address-cells = <1>;
 492                         #size-cells = <0>;
 493                         interrupts = <0 26 4>;
 494                         clocks = <&peri_clk 10>;
 495                         clock-frequency = <400000>;
 496                 };
 497
 498                 system_bus: system-bus@58c00000 {
 499                         compatible = "socionext,uniphier-system-bus";
 500                         status = "disabled";
 501                         reg = <0x58c00000 0x400>;
 502                         #address-cells = <2>;
 503                         #size-cells = <1>;
 504                         pinctrl-names = "default";
 505                         pinctrl-0 = <&pinctrl_system_bus>;
 506                 };
 507
 508                 smpctrl@59800000 {
 509                         compatible = "socionext,uniphier-smpctrl";
 510                         reg = <0x59801000 0x400>;
 511                 };
 512
 513                 sdctrl@59810000 {
 514                         compatible = "socionext,uniphier-pxs2-sdctrl",
 515                                      "simple-mfd", "syscon";
 516                         reg = <0x59810000 0x800>;
 517                         u-boot,dm-pre-reloc;
 518
 519                         sd_clk: clock {
 520                                 compatible = "socionext,uniphier-pxs2-sd-clock";
 521                                 #clock-cells = <1>;
 522                         };
 523
 524                         sd_rst: reset {
 525                                 compatible = "socionext,uniphier-pxs2-sd-reset";
 526                                 #reset-cells = <1>;
 527                         };
 528                 };
 529
 530                 perictrl@59820000 {
 531                         compatible = "socionext,uniphier-pxs2-perictrl",
 532                                      "simple-mfd", "syscon";
 533                         reg = <0x59820000 0x200>;
 534
 535                         peri_clk: clock {
 536                                 compatible = "socionext,uniphier-pxs2-peri-clock";
 537                                 #clock-cells = <1>;
 538                         };
 539
 540                         peri_rst: reset {
 541                                 compatible = "socionext,uniphier-pxs2-peri-reset";
 542                                 #reset-cells = <1>;
 543                         };
 544                 };
 545
 546                 emmc: sdhc@5a000000 {
 547                         compatible = "socionext,uniphier-sdhc";
 548                         status = "disabled";
 549                         reg = <0x5a000000 0x800>;
 550                         interrupts = <0 78 4>;
 551                         pinctrl-names = "default";
 552                         pinctrl-0 = <&pinctrl_emmc>;
 553                         clocks = <&sd_clk 1>;
 554                         reset-names = "host";
 555                         resets = <&sd_rst 1>;
 556                         bus-width = <8>;
 557                         non-removable;
 558                         cap-mmc-highspeed;
 559                         cap-mmc-hw-reset;
 560                         no-3-3-v;
 561                 };
 562
 563                 sd: sdhc@5a400000 {
 564                         compatible = "socionext,uniphier-sdhc";
 565                         status = "disabled";
 566                         reg = <0x5a400000 0x800>;
 567                         interrupts = <0 76 4>;
 568                         pinctrl-names = "default", "1.8v";
 569                         pinctrl-0 = <&pinctrl_sd>;
 570                         pinctrl-1 = <&pinctrl_sd_1v8>;
 571                         clocks = <&sd_clk 0>;
 572                         reset-names = "host";
 573                         resets = <&sd_rst 0>;
 574                         bus-width = <4>;
 575                         cap-sd-highspeed;
 576                         sd-uhs-sdr12;
 577                         sd-uhs-sdr25;
 578                         sd-uhs-sdr50;
 579                 };
 580
 581                 soc-glue@5f800000 {
 582                         compatible = "socionext,uniphier-pxs2-soc-glue",
 583                                      "simple-mfd", "syscon";
 584                         reg = <0x5f800000 0x2000>;
 585                         u-boot,dm-pre-reloc;
 586
 587                         pinctrl: pinctrl {
 588                                 compatible = "socionext,uniphier-pxs2-pinctrl";
 589                                 u-boot,dm-pre-reloc;
 590                         };
 591                 };
 592
 593                 aidet@5fc20000 {
 594                         compatible = "simple-mfd", "syscon";
 595                         reg = <0x5fc20000 0x200>;
 596                 };
 597
 598                 timer@60000200 {
 599                         compatible = "arm,cortex-a9-global-timer";
 600                         reg = <0x60000200 0x20>;
 601                         interrupts = <1 11 0xf04>;
 602                         clocks = <&arm_timer_clk>;
 603                 };
 604
 605                 timer@60000600 {
 606                         compatible = "arm,cortex-a9-twd-timer";
 607                         reg = <0x60000600 0x20>;
 608                         interrupts = <1 13 0xf04>;
 609                         clocks = <&arm_timer_clk>;
 610                 };
 611
 612                 intc: interrupt-controller@60001000 {
 613                         compatible = "arm,cortex-a9-gic";
 614                         reg = <0x60001000 0x1000>,
 615                               <0x60000100 0x100>;
 616                         #interrupt-cells = <3>;
 617                         interrupt-controller;
 618                 };
 619
 620                 sysctrl@61840000 {
 621                         compatible = "socionext,uniphier-pxs2-sysctrl",
 622                                      "simple-mfd", "syscon";
 623                         reg = <0x61840000 0x10000>;
 624
 625                         sys_clk: clock {
 626                                 compatible = "socionext,uniphier-pxs2-clock";
 627                                 #clock-cells = <1>;
 628                         };
 629
 630                         sys_rst: reset {
 631                                 compatible = "socionext,uniphier-pxs2-reset";
 632                                 #reset-cells = <1>;
 633                         };
 634                 };
 635
 636                 usb0: usb@65b00000 {
 637                         compatible = "socionext,uniphier-pxs2-dwc3";
 638                         status = "disabled";
 639                         reg = <0x65b00000 0x1000>;
 640                         #address-cells = <1>;
 641                         #size-cells = <1>;
 642                         ranges;
 643                         pinctrl-names = "default";
 644                         pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
 645                         dwc3@65a00000 {
 646                                 compatible = "snps,dwc3";
 647                                 reg = <0x65a00000 0x10000>;
 648                                 interrupts = <0 134 4>;
 649                                 tx-fifo-resize;
 650                         };
 651                 };
 652
 653                 usb1: usb@65d00000 {
 654                         compatible = "socionext,uniphier-pxs2-dwc3";
 655                         status = "disabled";
 656                         reg = <0x65d00000 0x1000>;
 657                         #address-cells = <1>;
 658                         #size-cells = <1>;
 659                         ranges;
 660                         pinctrl-names = "default";
 661                         pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
 662                         dwc3@65c00000 {
 663                                 compatible = "snps,dwc3";
 664                                 reg = <0x65c00000 0x10000>;
 665                                 interrupts = <0 137 4>;
 666                                 tx-fifo-resize;
 667                         };
 668                 };
 669
 670                 nand: nand@68000000 {
 671                         compatible = "socionext,uniphier-denali-nand-v5b";
 672                         status = "disabled";
 673                         reg-names = "nand_data", "denali_reg";
 674                         reg = <0x68000000 0x20>, <0x68100000 0x1000>;
 675                         interrupts = <0 65 4>;
 676                         pinctrl-names = "default";
 677                         pinctrl-0 = <&pinctrl_nand>;
 678                         clocks = <&sys_clk 2>;
 679                         nand-ecc-strength = <8>;
 680                 };
 681         };
 682 };
 683
 684 /include/ "uniphier-pinctrl.dtsi"