1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Device Tree Source for UniPhier PXs2 SoC
5 // Copyright (C) 2015-2016 Socionext Inc.
6 // Author: Masahiro Yamada <yamada.masahiro@socionext.com>
8 #include <dt-bindings/gpio/uniphier-gpio.h>
9 #include <dt-bindings/thermal/thermal.h>
12 compatible = "socionext,uniphier-pxs2";
22 compatible = "arm,cortex-a9";
24 clocks = <&sys_clk 32>;
25 enable-method = "psci";
26 next-level-cache = <&l2>;
27 operating-points-v2 = <&cpu_opp>;
33 compatible = "arm,cortex-a9";
35 clocks = <&sys_clk 32>;
36 enable-method = "psci";
37 next-level-cache = <&l2>;
38 operating-points-v2 = <&cpu_opp>;
43 compatible = "arm,cortex-a9";
45 clocks = <&sys_clk 32>;
46 enable-method = "psci";
47 next-level-cache = <&l2>;
48 operating-points-v2 = <&cpu_opp>;
53 compatible = "arm,cortex-a9";
55 clocks = <&sys_clk 32>;
56 enable-method = "psci";
57 next-level-cache = <&l2>;
58 operating-points-v2 = <&cpu_opp>;
63 compatible = "operating-points-v2";
67 opp-hz = /bits/ 64 <100000000>;
68 clock-latency-ns = <300>;
71 opp-hz = /bits/ 64 <150000000>;
72 clock-latency-ns = <300>;
75 opp-hz = /bits/ 64 <200000000>;
76 clock-latency-ns = <300>;
79 opp-hz = /bits/ 64 <300000000>;
80 clock-latency-ns = <300>;
83 opp-hz = /bits/ 64 <400000000>;
84 clock-latency-ns = <300>;
87 opp-hz = /bits/ 64 <600000000>;
88 clock-latency-ns = <300>;
91 opp-hz = /bits/ 64 <800000000>;
92 clock-latency-ns = <300>;
95 opp-hz = /bits/ 64 <1200000000>;
96 clock-latency-ns = <300>;
101 compatible = "arm,psci-0.2";
107 compatible = "fixed-clock";
109 clock-frequency = <25000000>;
112 arm_timer_clk: arm-timer {
114 compatible = "fixed-clock";
115 clock-frequency = <50000000>;
121 polling-delay-passive = <250>; /* 250ms */
122 polling-delay = <1000>; /* 1000ms */
123 thermal-sensors = <&pvtctl>;
127 temperature = <95000>; /* 95C */
131 cpu_alert: cpu-alert {
132 temperature = <85000>; /* 85C */
141 cooling-device = <&cpu0
142 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
149 compatible = "simple-bus";
150 #address-cells = <1>;
153 interrupt-parent = <&intc>;
155 l2: l2-cache@500c0000 {
156 compatible = "socionext,uniphier-system-cache";
157 reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
159 interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>;
161 cache-size = <(1280 * 1024)>;
163 cache-line-size = <128>;
167 serial0: serial@54006800 {
168 compatible = "socionext,uniphier-uart";
170 reg = <0x54006800 0x40>;
171 interrupts = <0 33 4>;
172 pinctrl-names = "default";
173 pinctrl-0 = <&pinctrl_uart0>;
174 clocks = <&peri_clk 0>;
175 clock-frequency = <88900000>;
176 resets = <&peri_rst 0>;
179 serial1: serial@54006900 {
180 compatible = "socionext,uniphier-uart";
182 reg = <0x54006900 0x40>;
183 interrupts = <0 35 4>;
184 pinctrl-names = "default";
185 pinctrl-0 = <&pinctrl_uart1>;
186 clocks = <&peri_clk 1>;
187 clock-frequency = <88900000>;
188 resets = <&peri_rst 1>;
191 serial2: serial@54006a00 {
192 compatible = "socionext,uniphier-uart";
194 reg = <0x54006a00 0x40>;
195 interrupts = <0 37 4>;
196 pinctrl-names = "default";
197 pinctrl-0 = <&pinctrl_uart2>;
198 clocks = <&peri_clk 2>;
199 clock-frequency = <88900000>;
200 resets = <&peri_rst 2>;
203 serial3: serial@54006b00 {
204 compatible = "socionext,uniphier-uart";
206 reg = <0x54006b00 0x40>;
207 interrupts = <0 177 4>;
208 pinctrl-names = "default";
209 pinctrl-0 = <&pinctrl_uart3>;
210 clocks = <&peri_clk 3>;
211 clock-frequency = <88900000>;
212 resets = <&peri_rst 3>;
215 gpio: gpio@55000000 {
216 compatible = "socionext,uniphier-gpio";
217 reg = <0x55000000 0x200>;
218 interrupt-parent = <&aidet>;
219 interrupt-controller;
220 #interrupt-cells = <2>;
223 gpio-ranges = <&pinctrl 0 0 0>,
225 gpio-ranges-group-names = "gpio_range0",
228 socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
233 compatible = "socionext,uniphier-pxs2-aio";
234 reg = <0x56000000 0x80000>;
235 interrupts = <0 144 4>;
236 pinctrl-names = "default";
237 pinctrl-0 = <&pinctrl_ain1>,
245 clocks = <&sys_clk 40>;
247 resets = <&sys_rst 40>;
248 #sound-dai-cells = <1>;
249 socionext,syscon = <&soc_glue>;
266 spdif_port0: port@3 {
267 spdif_hiecout1: endpoint {
271 spdif_port1: port@4 {
272 spdif_iecout1: endpoint {
276 comp_spdif_port0: port@5 {
277 comp_spdif_hiecout1: endpoint {
281 comp_spdif_port1: port@6 {
282 comp_spdif_iecout1: endpoint {
288 compatible = "socionext,uniphier-fi2c";
290 reg = <0x58780000 0x80>;
291 #address-cells = <1>;
293 interrupts = <0 41 4>;
294 pinctrl-names = "default";
295 pinctrl-0 = <&pinctrl_i2c0>;
296 clocks = <&peri_clk 4>;
297 resets = <&peri_rst 4>;
298 clock-frequency = <100000>;
302 compatible = "socionext,uniphier-fi2c";
304 reg = <0x58781000 0x80>;
305 #address-cells = <1>;
307 interrupts = <0 42 4>;
308 pinctrl-names = "default";
309 pinctrl-0 = <&pinctrl_i2c1>;
310 clocks = <&peri_clk 5>;
311 resets = <&peri_rst 5>;
312 clock-frequency = <100000>;
316 compatible = "socionext,uniphier-fi2c";
318 reg = <0x58782000 0x80>;
319 #address-cells = <1>;
321 interrupts = <0 43 4>;
322 pinctrl-names = "default";
323 pinctrl-0 = <&pinctrl_i2c2>;
324 clocks = <&peri_clk 6>;
325 resets = <&peri_rst 6>;
326 clock-frequency = <100000>;
330 compatible = "socionext,uniphier-fi2c";
332 reg = <0x58783000 0x80>;
333 #address-cells = <1>;
335 interrupts = <0 44 4>;
336 pinctrl-names = "default";
337 pinctrl-0 = <&pinctrl_i2c3>;
338 clocks = <&peri_clk 7>;
339 resets = <&peri_rst 7>;
340 clock-frequency = <100000>;
343 /* chip-internal connection for DMD */
345 compatible = "socionext,uniphier-fi2c";
346 reg = <0x58784000 0x80>;
347 #address-cells = <1>;
349 interrupts = <0 45 4>;
350 clocks = <&peri_clk 8>;
351 resets = <&peri_rst 8>;
352 clock-frequency = <400000>;
355 /* chip-internal connection for STM */
357 compatible = "socionext,uniphier-fi2c";
358 reg = <0x58785000 0x80>;
359 #address-cells = <1>;
361 interrupts = <0 25 4>;
362 clocks = <&peri_clk 9>;
363 resets = <&peri_rst 9>;
364 clock-frequency = <400000>;
367 /* chip-internal connection for HDMI */
369 compatible = "socionext,uniphier-fi2c";
370 reg = <0x58786000 0x80>;
371 #address-cells = <1>;
373 interrupts = <0 26 4>;
374 clocks = <&peri_clk 10>;
375 resets = <&peri_rst 10>;
376 clock-frequency = <400000>;
379 system_bus: system-bus@58c00000 {
380 compatible = "socionext,uniphier-system-bus";
382 reg = <0x58c00000 0x400>;
383 #address-cells = <2>;
385 pinctrl-names = "default";
386 pinctrl-0 = <&pinctrl_system_bus>;
390 compatible = "socionext,uniphier-smpctrl";
391 reg = <0x59801000 0x400>;
395 compatible = "socionext,uniphier-pxs2-sdctrl",
396 "simple-mfd", "syscon";
397 reg = <0x59810000 0x400>;
400 compatible = "socionext,uniphier-pxs2-sd-clock";
405 compatible = "socionext,uniphier-pxs2-sd-reset";
411 compatible = "socionext,uniphier-pxs2-perictrl",
412 "simple-mfd", "syscon";
413 reg = <0x59820000 0x200>;
416 compatible = "socionext,uniphier-pxs2-peri-clock";
421 compatible = "socionext,uniphier-pxs2-peri-reset";
426 emmc: sdhc@5a000000 {
427 compatible = "socionext,uniphier-sdhc";
429 reg = <0x5a000000 0x800>;
430 interrupts = <0 78 4>;
431 pinctrl-names = "default";
432 pinctrl-0 = <&pinctrl_emmc>;
433 clocks = <&sd_clk 1>;
434 reset-names = "host";
435 resets = <&sd_rst 1>;
444 compatible = "socionext,uniphier-sdhc";
446 reg = <0x5a400000 0x800>;
447 interrupts = <0 76 4>;
448 pinctrl-names = "default", "1.8v";
449 pinctrl-0 = <&pinctrl_sd>;
450 pinctrl-1 = <&pinctrl_sd_1v8>;
451 clocks = <&sd_clk 0>;
452 reset-names = "host";
453 resets = <&sd_rst 0>;
461 soc_glue: soc-glue@5f800000 {
462 compatible = "socionext,uniphier-pxs2-soc-glue",
463 "simple-mfd", "syscon";
464 reg = <0x5f800000 0x2000>;
467 compatible = "socionext,uniphier-pxs2-pinctrl";
472 compatible = "socionext,uniphier-pxs2-soc-glue-debug",
474 #address-cells = <1>;
476 ranges = <0 0x5f900000 0x2000>;
479 compatible = "socionext,uniphier-efuse";
484 compatible = "socionext,uniphier-efuse";
489 aidet: aidet@5fc20000 {
490 compatible = "socionext,uniphier-pxs2-aidet";
491 reg = <0x5fc20000 0x200>;
492 interrupt-controller;
493 #interrupt-cells = <2>;
497 compatible = "arm,cortex-a9-global-timer";
498 reg = <0x60000200 0x20>;
499 interrupts = <1 11 0xf04>;
500 clocks = <&arm_timer_clk>;
504 compatible = "arm,cortex-a9-twd-timer";
505 reg = <0x60000600 0x20>;
506 interrupts = <1 13 0xf04>;
507 clocks = <&arm_timer_clk>;
510 intc: interrupt-controller@60001000 {
511 compatible = "arm,cortex-a9-gic";
512 reg = <0x60001000 0x1000>,
514 #interrupt-cells = <3>;
515 interrupt-controller;
519 compatible = "socionext,uniphier-pxs2-sysctrl",
520 "simple-mfd", "syscon";
521 reg = <0x61840000 0x10000>;
524 compatible = "socionext,uniphier-pxs2-clock";
529 compatible = "socionext,uniphier-pxs2-reset";
534 compatible = "socionext,uniphier-pxs2-thermal";
535 interrupts = <0 3 4>;
536 #thermal-sensor-cells = <0>;
537 socionext,tmod-calibration = <0x0f86 0x6844>;
541 eth: ethernet@65000000 {
542 compatible = "socionext,uniphier-pxs2-ave4";
544 reg = <0x65000000 0x8500>;
545 interrupts = <0 66 4>;
546 pinctrl-names = "default";
547 pinctrl-0 = <&pinctrl_ether_rgmii>;
548 clocks = <&sys_clk 6>;
549 resets = <&sys_rst 6>;
551 local-mac-address = [00 00 00 00 00 00];
554 #address-cells = <1>;
560 compatible = "socionext,uniphier-pxs2-dwc3";
562 reg = <0x65b00000 0x1000>;
563 #address-cells = <1>;
566 pinctrl-names = "default";
567 pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
569 compatible = "snps,dwc3";
570 reg = <0x65a00000 0x10000>;
571 interrupts = <0 134 4>;
578 compatible = "socionext,uniphier-pxs2-dwc3";
580 reg = <0x65d00000 0x1000>;
581 #address-cells = <1>;
584 pinctrl-names = "default";
585 pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
587 compatible = "snps,dwc3";
588 reg = <0x65c00000 0x10000>;
589 interrupts = <0 137 4>;
595 nand: nand@68000000 {
596 compatible = "socionext,uniphier-denali-nand-v5b";
598 reg-names = "nand_data", "denali_reg";
599 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
600 interrupts = <0 65 4>;
601 pinctrl-names = "default";
602 pinctrl-0 = <&pinctrl_nand2cs>;
603 clocks = <&sys_clk 2>;
604 resets = <&sys_rst 2>;
609 #include "uniphier-pinctrl.dtsi"