git.sur5r.net Git - u-boot/blob - arch/arm/dts/uniphier-pxs2.dtsi

   1 /*
   2  * Device Tree Source for UniPhier PXs2 SoC
   3  *
   4  * Copyright (C) 2015-2016 Socionext Inc.
   5  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+        X11
   8  */
   9
  10 / {
  11         compatible = "socionext,uniphier-pxs2";
  12         #address-cells = <1>;
  13         #size-cells = <1>;
  14
  15         cpus {
  16                 #address-cells = <1>;
  17                 #size-cells = <0>;
  18
  19                 cpu@0 {
  20                         device_type = "cpu";
  21                         compatible = "arm,cortex-a9";
  22                         reg = <0>;
  23                         clocks = <&sys_clk 32>;
  24                         enable-method = "psci";
  25                         next-level-cache = <&l2>;
  26                         operating-points-v2 = <&cpu_opp>;
  27                 };
  28
  29                 cpu@1 {
  30                         device_type = "cpu";
  31                         compatible = "arm,cortex-a9";
  32                         reg = <1>;
  33                         clocks = <&sys_clk 32>;
  34                         enable-method = "psci";
  35                         next-level-cache = <&l2>;
  36                         operating-points-v2 = <&cpu_opp>;
  37                 };
  38
  39                 cpu@2 {
  40                         device_type = "cpu";
  41                         compatible = "arm,cortex-a9";
  42                         reg = <2>;
  43                         clocks = <&sys_clk 32>;
  44                         enable-method = "psci";
  45                         next-level-cache = <&l2>;
  46                         operating-points-v2 = <&cpu_opp>;
  47                 };
  48
  49                 cpu@3 {
  50                         device_type = "cpu";
  51                         compatible = "arm,cortex-a9";
  52                         reg = <3>;
  53                         clocks = <&sys_clk 32>;
  54                         enable-method = "psci";
  55                         next-level-cache = <&l2>;
  56                         operating-points-v2 = <&cpu_opp>;
  57                 };
  58         };
  59
  60         cpu_opp: opp_table {
  61                 compatible = "operating-points-v2";
  62                 opp-shared;
  63
  64                 opp@100000000 {
  65                         opp-hz = /bits/ 64 <100000000>;
  66                         clock-latency-ns = <300>;
  67                 };
  68                 opp@150000000 {
  69                         opp-hz = /bits/ 64 <150000000>;
  70                         clock-latency-ns = <300>;
  71                 };
  72                 opp@200000000 {
  73                         opp-hz = /bits/ 64 <200000000>;
  74                         clock-latency-ns = <300>;
  75                 };
  76                 opp@300000000 {
  77                         opp-hz = /bits/ 64 <300000000>;
  78                         clock-latency-ns = <300>;
  79                 };
  80                 opp@400000000 {
  81                         opp-hz = /bits/ 64 <400000000>;
  82                         clock-latency-ns = <300>;
  83                 };
  84                 opp@600000000 {
  85                         opp-hz = /bits/ 64 <600000000>;
  86                         clock-latency-ns = <300>;
  87                 };
  88                 opp@800000000 {
  89                         opp-hz = /bits/ 64 <800000000>;
  90                         clock-latency-ns = <300>;
  91                 };
  92                 opp@1200000000 {
  93                         opp-hz = /bits/ 64 <1200000000>;
  94                         clock-latency-ns = <300>;
  95                 };
  96         };
  97
  98         psci {
  99                 compatible = "arm,psci-0.2";
 100                 method = "smc";
 101         };
 102
 103         clocks {
 104                 refclk: ref {
 105                         compatible = "fixed-clock";
 106                         #clock-cells = <0>;
 107                         clock-frequency = <25000000>;
 108                 };
 109
 110                 arm_timer_clk: arm_timer_clk {
 111                         #clock-cells = <0>;
 112                         compatible = "fixed-clock";
 113                         clock-frequency = <50000000>;
 114                 };
 115         };
 116
 117         soc {
 118                 compatible = "simple-bus";
 119                 #address-cells = <1>;
 120                 #size-cells = <1>;
 121                 ranges;
 122                 interrupt-parent = <&intc>;
 123                 u-boot,dm-pre-reloc;
 124
 125                 l2: l2-cache@500c0000 {
 126                         compatible = "socionext,uniphier-system-cache";
 127                         reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
 128                               <0x506c0000 0x400>;
 129                         interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>;
 130                         cache-unified;
 131                         cache-size = <(1280 * 1024)>;
 132                         cache-sets = <512>;
 133                         cache-line-size = <128>;
 134                         cache-level = <2>;
 135                 };
 136
 137                 serial0: serial@54006800 {
 138                         compatible = "socionext,uniphier-uart";
 139                         status = "disabled";
 140                         reg = <0x54006800 0x40>;
 141                         interrupts = <0 33 4>;
 142                         pinctrl-names = "default";
 143                         pinctrl-0 = <&pinctrl_uart0>;
 144                         clocks = <&peri_clk 0>;
 145                         clock-frequency = <88900000>;
 146                 };
 147
 148                 serial1: serial@54006900 {
 149                         compatible = "socionext,uniphier-uart";
 150                         status = "disabled";
 151                         reg = <0x54006900 0x40>;
 152                         interrupts = <0 35 4>;
 153                         pinctrl-names = "default";
 154                         pinctrl-0 = <&pinctrl_uart1>;
 155                         clocks = <&peri_clk 1>;
 156                         clock-frequency = <88900000>;
 157                 };
 158
 159                 serial2: serial@54006a00 {
 160                         compatible = "socionext,uniphier-uart";
 161                         status = "disabled";
 162                         reg = <0x54006a00 0x40>;
 163                         interrupts = <0 37 4>;
 164                         pinctrl-names = "default";
 165                         pinctrl-0 = <&pinctrl_uart2>;
 166                         clocks = <&peri_clk 2>;
 167                         clock-frequency = <88900000>;
 168                 };
 169
 170                 serial3: serial@54006b00 {
 171                         compatible = "socionext,uniphier-uart";
 172                         status = "disabled";
 173                         reg = <0x54006b00 0x40>;
 174                         interrupts = <0 177 4>;
 175                         pinctrl-names = "default";
 176                         pinctrl-0 = <&pinctrl_uart3>;
 177                         clocks = <&peri_clk 3>;
 178                         clock-frequency = <88900000>;
 179                 };
 180
 181                 port0x: gpio@55000008 {
 182                         compatible = "socionext,uniphier-gpio";
 183                         reg = <0x55000008 0x8>;
 184                         gpio-controller;
 185                         #gpio-cells = <2>;
 186                 };
 187
 188                 port1x: gpio@55000010 {
 189                         compatible = "socionext,uniphier-gpio";
 190                         reg = <0x55000010 0x8>;
 191                         gpio-controller;
 192                         #gpio-cells = <2>;
 193                 };
 194
 195                 port2x: gpio@55000018 {
 196                         compatible = "socionext,uniphier-gpio";
 197                         reg = <0x55000018 0x8>;
 198                         gpio-controller;
 199                         #gpio-cells = <2>;
 200                 };
 201
 202                 port3x: gpio@55000020 {
 203                         compatible = "socionext,uniphier-gpio";
 204                         reg = <0x55000020 0x8>;
 205                         gpio-controller;
 206                         #gpio-cells = <2>;
 207                 };
 208
 209                 port4: gpio@55000028 {
 210                         compatible = "socionext,uniphier-gpio";
 211                         reg = <0x55000028 0x8>;
 212                         gpio-controller;
 213                         #gpio-cells = <2>;
 214                 };
 215
 216                 port5x: gpio@55000030 {
 217                         compatible = "socionext,uniphier-gpio";
 218                         reg = <0x55000030 0x8>;
 219                         gpio-controller;
 220                         #gpio-cells = <2>;
 221                 };
 222
 223                 port6x: gpio@55000038 {
 224                         compatible = "socionext,uniphier-gpio";
 225                         reg = <0x55000038 0x8>;
 226                         gpio-controller;
 227                         #gpio-cells = <2>;
 228                 };
 229
 230                 port7x: gpio@55000040 {
 231                         compatible = "socionext,uniphier-gpio";
 232                         reg = <0x55000040 0x8>;
 233                         gpio-controller;
 234                         #gpio-cells = <2>;
 235                 };
 236
 237                 port8x: gpio@55000048 {
 238                         compatible = "socionext,uniphier-gpio";
 239                         reg = <0x55000048 0x8>;
 240                         gpio-controller;
 241                         #gpio-cells = <2>;
 242                 };
 243
 244                 port9x: gpio@55000050 {
 245                         compatible = "socionext,uniphier-gpio";
 246                         reg = <0x55000050 0x8>;
 247                         gpio-controller;
 248                         #gpio-cells = <2>;
 249                 };
 250
 251                 port10x: gpio@55000058 {
 252                         compatible = "socionext,uniphier-gpio";
 253                         reg = <0x55000058 0x8>;
 254                         gpio-controller;
 255                         #gpio-cells = <2>;
 256                 };
 257
 258                 port12x: gpio@55000068 {
 259                         compatible = "socionext,uniphier-gpio";
 260                         reg = <0x55000068 0x8>;
 261                         gpio-controller;
 262                         #gpio-cells = <2>;
 263                 };
 264
 265                 port13x: gpio@55000070 {
 266                         compatible = "socionext,uniphier-gpio";
 267                         reg = <0x55000070 0x8>;
 268                         gpio-controller;
 269                         #gpio-cells = <2>;
 270                 };
 271
 272                 port14x: gpio@55000078 {
 273                         compatible = "socionext,uniphier-gpio";
 274                         reg = <0x55000078 0x8>;
 275                         gpio-controller;
 276                         #gpio-cells = <2>;
 277                 };
 278
 279                 port15x: gpio@55000080 {
 280                         compatible = "socionext,uniphier-gpio";
 281                         reg = <0x55000080 0x8>;
 282                         gpio-controller;
 283                         #gpio-cells = <2>;
 284                 };
 285
 286                 port16x: gpio@55000088 {
 287                         compatible = "socionext,uniphier-gpio";
 288                         reg = <0x55000088 0x8>;
 289                         gpio-controller;
 290                         #gpio-cells = <2>;
 291                 };
 292
 293                 port17x: gpio@550000a0 {
 294                         compatible = "socionext,uniphier-gpio";
 295                         reg = <0x550000a0 0x8>;
 296                         gpio-controller;
 297                         #gpio-cells = <2>;
 298                 };
 299
 300                 port18x: gpio@550000a8 {
 301                         compatible = "socionext,uniphier-gpio";
 302                         reg = <0x550000a8 0x8>;
 303                         gpio-controller;
 304                         #gpio-cells = <2>;
 305                 };
 306
 307                 port19x: gpio@550000b0 {
 308                         compatible = "socionext,uniphier-gpio";
 309                         reg = <0x550000b0 0x8>;
 310                         gpio-controller;
 311                         #gpio-cells = <2>;
 312                 };
 313
 314                 port20x: gpio@550000b8 {
 315                         compatible = "socionext,uniphier-gpio";
 316                         reg = <0x550000b8 0x8>;
 317                         gpio-controller;
 318                         #gpio-cells = <2>;
 319                 };
 320
 321                 port21x: gpio@550000c0 {
 322                         compatible = "socionext,uniphier-gpio";
 323                         reg = <0x550000c0 0x8>;
 324                         gpio-controller;
 325                         #gpio-cells = <2>;
 326                 };
 327
 328                 port22x: gpio@550000c8 {
 329                         compatible = "socionext,uniphier-gpio";
 330                         reg = <0x550000c8 0x8>;
 331                         gpio-controller;
 332                         #gpio-cells = <2>;
 333                 };
 334
 335                 port23x: gpio@550000d0 {
 336                         compatible = "socionext,uniphier-gpio";
 337                         reg = <0x550000d0 0x8>;
 338                         gpio-controller;
 339                         #gpio-cells = <2>;
 340                 };
 341
 342                 port24x: gpio@550000d8 {
 343                         compatible = "socionext,uniphier-gpio";
 344                         reg = <0x550000d8 0x8>;
 345                         gpio-controller;
 346                         #gpio-cells = <2>;
 347                 };
 348
 349                 port25x: gpio@550000e0 {
 350                         compatible = "socionext,uniphier-gpio";
 351                         reg = <0x550000e0 0x8>;
 352                         gpio-controller;
 353                         #gpio-cells = <2>;
 354                 };
 355
 356                 port26x: gpio@550000e8 {
 357                         compatible = "socionext,uniphier-gpio";
 358                         reg = <0x550000e8 0x8>;
 359                         gpio-controller;
 360                         #gpio-cells = <2>;
 361                 };
 362
 363                 port27x: gpio@550000f0 {
 364                         compatible = "socionext,uniphier-gpio";
 365                         reg = <0x550000f0 0x8>;
 366                         gpio-controller;
 367                         #gpio-cells = <2>;
 368                 };
 369
 370                 port28x: gpio@550000f8 {
 371                         compatible = "socionext,uniphier-gpio";
 372                         reg = <0x550000f8 0x8>;
 373                         gpio-controller;
 374                         #gpio-cells = <2>;
 375                 };
 376
 377                 i2c0: i2c@58780000 {
 378                         compatible = "socionext,uniphier-fi2c";
 379                         status = "disabled";
 380                         reg = <0x58780000 0x80>;
 381                         #address-cells = <1>;
 382                         #size-cells = <0>;
 383                         interrupts = <0 41 4>;
 384                         pinctrl-names = "default";
 385                         pinctrl-0 = <&pinctrl_i2c0>;
 386                         clocks = <&peri_clk 4>;
 387                         clock-frequency = <100000>;
 388                 };
 389
 390                 i2c1: i2c@58781000 {
 391                         compatible = "socionext,uniphier-fi2c";
 392                         status = "disabled";
 393                         reg = <0x58781000 0x80>;
 394                         #address-cells = <1>;
 395                         #size-cells = <0>;
 396                         interrupts = <0 42 4>;
 397                         pinctrl-names = "default";
 398                         pinctrl-0 = <&pinctrl_i2c1>;
 399                         clocks = <&peri_clk 5>;
 400                         clock-frequency = <100000>;
 401                 };
 402
 403                 i2c2: i2c@58782000 {
 404                         compatible = "socionext,uniphier-fi2c";
 405                         status = "disabled";
 406                         reg = <0x58782000 0x80>;
 407                         #address-cells = <1>;
 408                         #size-cells = <0>;
 409                         interrupts = <0 43 4>;
 410                         pinctrl-names = "default";
 411                         pinctrl-0 = <&pinctrl_i2c2>;
 412                         clocks = <&peri_clk 6>;
 413                         clock-frequency = <100000>;
 414                 };
 415
 416                 i2c3: i2c@58783000 {
 417                         compatible = "socionext,uniphier-fi2c";
 418                         status = "disabled";
 419                         reg = <0x58783000 0x80>;
 420                         #address-cells = <1>;
 421                         #size-cells = <0>;
 422                         interrupts = <0 44 4>;
 423                         pinctrl-names = "default";
 424                         pinctrl-0 = <&pinctrl_i2c3>;
 425                         clocks = <&peri_clk 7>;
 426                         clock-frequency = <100000>;
 427                 };
 428
 429                 /* chip-internal connection for DMD */
 430                 i2c4: i2c@58784000 {
 431                         compatible = "socionext,uniphier-fi2c";
 432                         reg = <0x58784000 0x80>;
 433                         #address-cells = <1>;
 434                         #size-cells = <0>;
 435                         interrupts = <0 45 4>;
 436                         clocks = <&peri_clk 8>;
 437                         clock-frequency = <400000>;
 438                 };
 439
 440                 /* chip-internal connection for STM */
 441                 i2c5: i2c@58785000 {
 442                         compatible = "socionext,uniphier-fi2c";
 443                         reg = <0x58785000 0x80>;
 444                         #address-cells = <1>;
 445                         #size-cells = <0>;
 446                         interrupts = <0 25 4>;
 447                         clocks = <&peri_clk 9>;
 448                         clock-frequency = <400000>;
 449                 };
 450
 451                 /* chip-internal connection for HDMI */
 452                 i2c6: i2c@58786000 {
 453                         compatible = "socionext,uniphier-fi2c";
 454                         reg = <0x58786000 0x80>;
 455                         #address-cells = <1>;
 456                         #size-cells = <0>;
 457                         interrupts = <0 26 4>;
 458                         clocks = <&peri_clk 10>;
 459                         clock-frequency = <400000>;
 460                 };
 461
 462                 system_bus: system-bus@58c00000 {
 463                         compatible = "socionext,uniphier-system-bus";
 464                         status = "disabled";
 465                         reg = <0x58c00000 0x400>;
 466                         #address-cells = <2>;
 467                         #size-cells = <1>;
 468                         pinctrl-names = "default";
 469                         pinctrl-0 = <&pinctrl_system_bus>;
 470                 };
 471
 472                 smpctrl@59800000 {
 473                         compatible = "socionext,uniphier-smpctrl";
 474                         reg = <0x59801000 0x400>;
 475                 };
 476
 477                 sdctrl@59810000 {
 478                         compatible = "socionext,uniphier-pxs2-sdctrl",
 479                                      "simple-mfd", "syscon";
 480                         reg = <0x59810000 0x800>;
 481                         u-boot,dm-pre-reloc;
 482
 483                         sd_clk: clock {
 484                                 compatible = "socionext,uniphier-pxs2-sd-clock";
 485                                 #clock-cells = <1>;
 486                         };
 487
 488                         sd_rst: reset {
 489                                 compatible = "socionext,uniphier-pxs2-sd-reset";
 490                                 #reset-cells = <1>;
 491                         };
 492                 };
 493
 494                 perictrl@59820000 {
 495                         compatible = "socionext,uniphier-pxs2-perictrl",
 496                                      "simple-mfd", "syscon";
 497                         reg = <0x59820000 0x200>;
 498
 499                         peri_clk: clock {
 500                                 compatible = "socionext,uniphier-pxs2-peri-clock";
 501                                 #clock-cells = <1>;
 502                         };
 503
 504                         peri_rst: reset {
 505                                 compatible = "socionext,uniphier-pxs2-peri-reset";
 506                                 #reset-cells = <1>;
 507                         };
 508                 };
 509
 510                 emmc: sdhc@5a000000 {
 511                         compatible = "socionext,uniphier-sdhc";
 512                         status = "disabled";
 513                         reg = <0x5a000000 0x800>;
 514                         interrupts = <0 78 4>;
 515                         pinctrl-names = "default";
 516                         pinctrl-0 = <&pinctrl_emmc>;
 517                         clocks = <&sd_clk 1>;
 518                         reset-names = "host";
 519                         resets = <&sd_rst 1>;
 520                         bus-width = <8>;
 521                         non-removable;
 522                         cap-mmc-highspeed;
 523                         cap-mmc-hw-reset;
 524                         no-3-3-v;
 525                 };
 526
 527                 sd: sdhc@5a400000 {
 528                         compatible = "socionext,uniphier-sdhc";
 529                         status = "disabled";
 530                         reg = <0x5a400000 0x800>;
 531                         interrupts = <0 76 4>;
 532                         pinctrl-names = "default", "1.8v";
 533                         pinctrl-0 = <&pinctrl_sd>;
 534                         pinctrl-1 = <&pinctrl_sd_1v8>;
 535                         clocks = <&sd_clk 0>;
 536                         reset-names = "host";
 537                         resets = <&sd_rst 0>;
 538                         bus-width = <4>;
 539                         cap-sd-highspeed;
 540                         sd-uhs-sdr12;
 541                         sd-uhs-sdr25;
 542                         sd-uhs-sdr50;
 543                 };
 544
 545                 soc-glue@5f800000 {
 546                         compatible = "socionext,uniphier-pxs2-soc-glue",
 547                                      "simple-mfd", "syscon";
 548                         reg = <0x5f800000 0x2000>;
 549                         u-boot,dm-pre-reloc;
 550
 551                         pinctrl: pinctrl {
 552                                 compatible = "socionext,uniphier-pxs2-pinctrl";
 553                                 u-boot,dm-pre-reloc;
 554                         };
 555                 };
 556
 557                 aidet@5fc20000 {
 558                         compatible = "simple-mfd", "syscon";
 559                         reg = <0x5fc20000 0x200>;
 560                 };
 561
 562                 timer@60000200 {
 563                         compatible = "arm,cortex-a9-global-timer";
 564                         reg = <0x60000200 0x20>;
 565                         interrupts = <1 11 0xf04>;
 566                         clocks = <&arm_timer_clk>;
 567                 };
 568
 569                 timer@60000600 {
 570                         compatible = "arm,cortex-a9-twd-timer";
 571                         reg = <0x60000600 0x20>;
 572                         interrupts = <1 13 0xf04>;
 573                         clocks = <&arm_timer_clk>;
 574                 };
 575
 576                 intc: interrupt-controller@60001000 {
 577                         compatible = "arm,cortex-a9-gic";
 578                         reg = <0x60001000 0x1000>,
 579                               <0x60000100 0x100>;
 580                         #interrupt-cells = <3>;
 581                         interrupt-controller;
 582                 };
 583
 584                 sysctrl@61840000 {
 585                         compatible = "socionext,uniphier-pxs2-sysctrl",
 586                                      "simple-mfd", "syscon";
 587                         reg = <0x61840000 0x10000>;
 588
 589                         sys_clk: clock {
 590                                 compatible = "socionext,uniphier-pxs2-clock";
 591                                 #clock-cells = <1>;
 592                         };
 593
 594                         sys_rst: reset {
 595                                 compatible = "socionext,uniphier-pxs2-reset";
 596                                 #reset-cells = <1>;
 597                         };
 598                 };
 599
 600                 usb0: usb@65b00000 {
 601                         compatible = "socionext,uniphier-pxs2-dwc3";
 602                         status = "disabled";
 603                         reg = <0x65b00000 0x1000>;
 604                         #address-cells = <1>;
 605                         #size-cells = <1>;
 606                         ranges;
 607                         pinctrl-names = "default";
 608                         pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
 609                         dwc3@65a00000 {
 610                                 compatible = "snps,dwc3";
 611                                 reg = <0x65a00000 0x10000>;
 612                                 interrupts = <0 134 4>;
 613                                 tx-fifo-resize;
 614                         };
 615                 };
 616
 617                 usb1: usb@65d00000 {
 618                         compatible = "socionext,uniphier-pxs2-dwc3";
 619                         status = "disabled";
 620                         reg = <0x65d00000 0x1000>;
 621                         #address-cells = <1>;
 622                         #size-cells = <1>;
 623                         ranges;
 624                         pinctrl-names = "default";
 625                         pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
 626                         dwc3@65c00000 {
 627                                 compatible = "snps,dwc3";
 628                                 reg = <0x65c00000 0x10000>;
 629                                 interrupts = <0 137 4>;
 630                                 tx-fifo-resize;
 631                         };
 632                 };
 633
 634                 nand: nand@68000000 {
 635                         compatible = "socionext,denali-nand-v5b";
 636                         status = "disabled";
 637                         reg-names = "nand_data", "denali_reg";
 638                         reg = <0x68000000 0x20>, <0x68100000 0x1000>;
 639                         interrupts = <0 65 4>;
 640                         pinctrl-names = "default";
 641                         pinctrl-0 = <&pinctrl_nand>;
 642                         clocks = <&sys_clk 2>;
 643                         nand-ecc-strength = <8>;
 644                 };
 645         };
 646 };
 647
 648 /include/ "uniphier-pinctrl.dtsi"