git.sur5r.net Git - u-boot/blob - arch/arm/dts/uniphier-pxs2.dtsi

   1 /*
   2  * Device Tree Source for UniPhier PXs2 SoC
   3  *
   4  * Copyright (C) 2015-2016 Socionext Inc.
   5  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+        X11
   8  */
   9
  10 /include/ "uniphier-common32.dtsi"
  11
  12 / {
  13         compatible = "socionext,uniphier-pxs2";
  14
  15         cpus {
  16                 #address-cells = <1>;
  17                 #size-cells = <0>;
  18
  19                 cpu@0 {
  20                         device_type = "cpu";
  21                         compatible = "arm,cortex-a9";
  22                         reg = <0>;
  23                         enable-method = "psci";
  24                         next-level-cache = <&l2>;
  25                 };
  26
  27                 cpu@1 {
  28                         device_type = "cpu";
  29                         compatible = "arm,cortex-a9";
  30                         reg = <1>;
  31                         enable-method = "psci";
  32                         next-level-cache = <&l2>;
  33                 };
  34
  35                 cpu@2 {
  36                         device_type = "cpu";
  37                         compatible = "arm,cortex-a9";
  38                         reg = <2>;
  39                         enable-method = "psci";
  40                         next-level-cache = <&l2>;
  41                 };
  42
  43                 cpu@3 {
  44                         device_type = "cpu";
  45                         compatible = "arm,cortex-a9";
  46                         reg = <3>;
  47                         enable-method = "psci";
  48                         next-level-cache = <&l2>;
  49                 };
  50         };
  51
  52         clocks {
  53                 arm_timer_clk: arm_timer_clk {
  54                         #clock-cells = <0>;
  55                         compatible = "fixed-clock";
  56                         clock-frequency = <50000000>;
  57                 };
  58
  59                 i2c_clk: i2c_clk {
  60                         #clock-cells = <0>;
  61                         compatible = "fixed-clock";
  62                         clock-frequency = <50000000>;
  63                 };
  64         };
  65 };
  66
  67 &soc {
  68         l2: l2-cache@500c0000 {
  69                 compatible = "socionext,uniphier-system-cache";
  70                 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>;
  71                 interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>;
  72                 cache-unified;
  73                 cache-size = <(1280 * 1024)>;
  74                 cache-sets = <512>;
  75                 cache-line-size = <128>;
  76                 cache-level = <2>;
  77         };
  78
  79         port0x: gpio@55000008 {
  80                 compatible = "socionext,uniphier-gpio";
  81                 reg = <0x55000008 0x8>;
  82                 gpio-controller;
  83                 #gpio-cells = <2>;
  84         };
  85
  86         port1x: gpio@55000010 {
  87                 compatible = "socionext,uniphier-gpio";
  88                 reg = <0x55000010 0x8>;
  89                 gpio-controller;
  90                 #gpio-cells = <2>;
  91         };
  92
  93         port2x: gpio@55000018 {
  94                 compatible = "socionext,uniphier-gpio";
  95                 reg = <0x55000018 0x8>;
  96                 gpio-controller;
  97                 #gpio-cells = <2>;
  98         };
  99
 100         port3x: gpio@55000020 {
 101                 compatible = "socionext,uniphier-gpio";
 102                 reg = <0x55000020 0x8>;
 103                 gpio-controller;
 104                 #gpio-cells = <2>;
 105         };
 106
 107         port4: gpio@55000028 {
 108                 compatible = "socionext,uniphier-gpio";
 109                 reg = <0x55000028 0x8>;
 110                 gpio-controller;
 111                 #gpio-cells = <2>;
 112         };
 113
 114         port5x: gpio@55000030 {
 115                 compatible = "socionext,uniphier-gpio";
 116                 reg = <0x55000030 0x8>;
 117                 gpio-controller;
 118                 #gpio-cells = <2>;
 119         };
 120
 121         port6x: gpio@55000038 {
 122                 compatible = "socionext,uniphier-gpio";
 123                 reg = <0x55000038 0x8>;
 124                 gpio-controller;
 125                 #gpio-cells = <2>;
 126         };
 127
 128         port7x: gpio@55000040 {
 129                 compatible = "socionext,uniphier-gpio";
 130                 reg = <0x55000040 0x8>;
 131                 gpio-controller;
 132                 #gpio-cells = <2>;
 133         };
 134
 135         port8x: gpio@55000048 {
 136                 compatible = "socionext,uniphier-gpio";
 137                 reg = <0x55000048 0x8>;
 138                 gpio-controller;
 139                 #gpio-cells = <2>;
 140         };
 141
 142         port9x: gpio@55000050 {
 143                 compatible = "socionext,uniphier-gpio";
 144                 reg = <0x55000050 0x8>;
 145                 gpio-controller;
 146                 #gpio-cells = <2>;
 147         };
 148
 149         port10x: gpio@55000058 {
 150                 compatible = "socionext,uniphier-gpio";
 151                 reg = <0x55000058 0x8>;
 152                 gpio-controller;
 153                 #gpio-cells = <2>;
 154         };
 155
 156         port12x: gpio@55000068 {
 157                 compatible = "socionext,uniphier-gpio";
 158                 reg = <0x55000068 0x8>;
 159                 gpio-controller;
 160                 #gpio-cells = <2>;
 161         };
 162
 163         port13x: gpio@55000070 {
 164                 compatible = "socionext,uniphier-gpio";
 165                 reg = <0x55000070 0x8>;
 166                 gpio-controller;
 167                 #gpio-cells = <2>;
 168         };
 169
 170         port14x: gpio@55000078 {
 171                 compatible = "socionext,uniphier-gpio";
 172                 reg = <0x55000078 0x8>;
 173                 gpio-controller;
 174                 #gpio-cells = <2>;
 175         };
 176
 177         port15x: gpio@55000080 {
 178                 compatible = "socionext,uniphier-gpio";
 179                 reg = <0x55000080 0x8>;
 180                 gpio-controller;
 181                 #gpio-cells = <2>;
 182         };
 183
 184         port16x: gpio@55000088 {
 185                 compatible = "socionext,uniphier-gpio";
 186                 reg = <0x55000088 0x8>;
 187                 gpio-controller;
 188                 #gpio-cells = <2>;
 189         };
 190
 191         port17x: gpio@550000a0 {
 192                 compatible = "socionext,uniphier-gpio";
 193                 reg = <0x550000a0 0x8>;
 194                 gpio-controller;
 195                 #gpio-cells = <2>;
 196         };
 197
 198         port18x: gpio@550000a8 {
 199                 compatible = "socionext,uniphier-gpio";
 200                 reg = <0x550000a8 0x8>;
 201                 gpio-controller;
 202                 #gpio-cells = <2>;
 203         };
 204
 205         port19x: gpio@550000b0 {
 206                 compatible = "socionext,uniphier-gpio";
 207                 reg = <0x550000b0 0x8>;
 208                 gpio-controller;
 209                 #gpio-cells = <2>;
 210         };
 211
 212         port20x: gpio@550000b8 {
 213                 compatible = "socionext,uniphier-gpio";
 214                 reg = <0x550000b8 0x8>;
 215                 gpio-controller;
 216                 #gpio-cells = <2>;
 217         };
 218
 219         port21x: gpio@550000c0 {
 220                 compatible = "socionext,uniphier-gpio";
 221                 reg = <0x550000c0 0x8>;
 222                 gpio-controller;
 223                 #gpio-cells = <2>;
 224         };
 225
 226         port22x: gpio@550000c8 {
 227                 compatible = "socionext,uniphier-gpio";
 228                 reg = <0x550000c8 0x8>;
 229                 gpio-controller;
 230                 #gpio-cells = <2>;
 231         };
 232
 233         port23x: gpio@550000d0 {
 234                 compatible = "socionext,uniphier-gpio";
 235                 reg = <0x550000d0 0x8>;
 236                 gpio-controller;
 237                 #gpio-cells = <2>;
 238         };
 239
 240         port24x: gpio@550000d8 {
 241                 compatible = "socionext,uniphier-gpio";
 242                 reg = <0x550000d8 0x8>;
 243                 gpio-controller;
 244                 #gpio-cells = <2>;
 245         };
 246
 247         port25x: gpio@550000e0 {
 248                 compatible = "socionext,uniphier-gpio";
 249                 reg = <0x550000e0 0x8>;
 250                 gpio-controller;
 251                 #gpio-cells = <2>;
 252         };
 253
 254         port26x: gpio@550000e8 {
 255                 compatible = "socionext,uniphier-gpio";
 256                 reg = <0x550000e8 0x8>;
 257                 gpio-controller;
 258                 #gpio-cells = <2>;
 259         };
 260
 261         port27x: gpio@550000f0 {
 262                 compatible = "socionext,uniphier-gpio";
 263                 reg = <0x550000f0 0x8>;
 264                 gpio-controller;
 265                 #gpio-cells = <2>;
 266         };
 267
 268         port28x: gpio@550000f8 {
 269                 compatible = "socionext,uniphier-gpio";
 270                 reg = <0x550000f8 0x8>;
 271                 gpio-controller;
 272                 #gpio-cells = <2>;
 273         };
 274
 275         i2c0: i2c@58780000 {
 276                 compatible = "socionext,uniphier-fi2c";
 277                 status = "disabled";
 278                 reg = <0x58780000 0x80>;
 279                 #address-cells = <1>;
 280                 #size-cells = <0>;
 281                 interrupts = <0 41 4>;
 282                 pinctrl-names = "default";
 283                 pinctrl-0 = <&pinctrl_i2c0>;
 284                 clocks = <&i2c_clk>;
 285                 clock-frequency = <100000>;
 286         };
 287
 288         i2c1: i2c@58781000 {
 289                 compatible = "socionext,uniphier-fi2c";
 290                 status = "disabled";
 291                 reg = <0x58781000 0x80>;
 292                 #address-cells = <1>;
 293                 #size-cells = <0>;
 294                 interrupts = <0 42 4>;
 295                 pinctrl-names = "default";
 296                 pinctrl-0 = <&pinctrl_i2c1>;
 297                 clocks = <&i2c_clk>;
 298                 clock-frequency = <100000>;
 299         };
 300
 301         i2c2: i2c@58782000 {
 302                 compatible = "socionext,uniphier-fi2c";
 303                 status = "disabled";
 304                 reg = <0x58782000 0x80>;
 305                 #address-cells = <1>;
 306                 #size-cells = <0>;
 307                 pinctrl-names = "default";
 308                 pinctrl-0 = <&pinctrl_i2c2>;
 309                 interrupts = <0 43 4>;
 310                 clocks = <&i2c_clk>;
 311                 clock-frequency = <100000>;
 312         };
 313
 314         i2c3: i2c@58783000 {
 315                 compatible = "socionext,uniphier-fi2c";
 316                 status = "disabled";
 317                 reg = <0x58783000 0x80>;
 318                 #address-cells = <1>;
 319                 #size-cells = <0>;
 320                 interrupts = <0 44 4>;
 321                 pinctrl-names = "default";
 322                 pinctrl-0 = <&pinctrl_i2c3>;
 323                 clocks = <&i2c_clk>;
 324                 clock-frequency = <100000>;
 325         };
 326
 327         /* chip-internal connection for DMD */
 328         i2c4: i2c@58784000 {
 329                 compatible = "socionext,uniphier-fi2c";
 330                 reg = <0x58784000 0x80>;
 331                 #address-cells = <1>;
 332                 #size-cells = <0>;
 333                 interrupts = <0 45 4>;
 334                 clocks = <&i2c_clk>;
 335                 clock-frequency = <400000>;
 336         };
 337
 338         /* chip-internal connection for STM */
 339         i2c5: i2c@58785000 {
 340                 compatible = "socionext,uniphier-fi2c";
 341                 reg = <0x58785000 0x80>;
 342                 #address-cells = <1>;
 343                 #size-cells = <0>;
 344                 interrupts = <0 25 4>;
 345                 clocks = <&i2c_clk>;
 346                 clock-frequency = <400000>;
 347         };
 348
 349         /* chip-internal connection for HDMI */
 350         i2c6: i2c@58786000 {
 351                 compatible = "socionext,uniphier-fi2c";
 352                 reg = <0x58786000 0x80>;
 353                 #address-cells = <1>;
 354                 #size-cells = <0>;
 355                 interrupts = <0 26 4>;
 356                 clocks = <&i2c_clk>;
 357                 clock-frequency = <400000>;
 358         };
 359
 360         emmc: sdhc@5a000000 {
 361                 compatible = "socionext,uniphier-sdhc";
 362                 status = "disabled";
 363                 reg = <0x5a000000 0x800>;
 364                 interrupts = <0 78 4>;
 365                 pinctrl-names = "default";
 366                 pinctrl-0 = <&pinctrl_emmc>;
 367                 clocks = <&mio_clk 1>;
 368                 reset-names = "host", "hw-reset";
 369                 resets = <&mio_rst 1>, <&mio_rst 6>;
 370                 bus-width = <8>;
 371                 non-removable;
 372         };
 373
 374         sd: sdhc@5a400000 {
 375                 compatible = "socionext,uniphier-sdhc";
 376                 status = "disabled";
 377                 reg = <0x5a400000 0x800>;
 378                 interrupts = <0 76 4>;
 379                 pinctrl-names = "default", "1.8v";
 380                 pinctrl-0 = <&pinctrl_sd>;
 381                 pinctrl-1 = <&pinctrl_sd_1v8>;
 382                 clocks = <&mio_clk 0>;
 383                 reset-names = "host";
 384                 resets = <&mio_rst 0>;
 385                 bus-width = <4>;
 386         };
 387
 388         aidet@5fc20000 {
 389                 compatible = "simple-mfd", "syscon";
 390                 reg = <0x5fc20000 0x200>;
 391         };
 392
 393         usb0: usb@65a00000 {
 394                 compatible = "socionext,uniphier-xhci", "generic-xhci";
 395                 status = "disabled";
 396                 reg = <0x65a00000 0x100>;
 397                 interrupts = <0 134 4>;
 398                 pinctrl-names = "default";
 399                 pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
 400         };
 401
 402         usb1: usb@65c00000 {
 403                 compatible = "socionext,uniphier-xhci", "generic-xhci";
 404                 status = "disabled";
 405                 reg = <0x65c00000 0x100>;
 406                 interrupts = <0 137 4>;
 407                 pinctrl-names = "default";
 408                 pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
 409         };
 410 };
 411
 412 &refclk {
 413         clock-frequency = <25000000>;
 414 };
 415
 416 &serial0 {
 417         clock-frequency = <88900000>;
 418 };
 419
 420 &serial1 {
 421         clock-frequency = <88900000>;
 422 };
 423
 424 &serial2 {
 425         clock-frequency = <88900000>;
 426 };
 427
 428 &serial3 {
 429         clock-frequency = <88900000>;
 430 };
 431
 432 &mio_clk {
 433         compatible = "socionext,uniphier-pxs2-mio-clock";
 434 };
 435
 436 &mio_rst {
 437         compatible = "socionext,uniphier-pxs2-mio-reset";
 438 };
 439
 440 &peri_clk {
 441         compatible = "socionext,uniphier-pxs2-peri-clock";
 442 };
 443
 444 &peri_rst {
 445         compatible = "socionext,uniphier-pxs2-peri-reset";
 446 };
 447
 448 &pinctrl {
 449         compatible = "socionext,uniphier-pxs2-pinctrl";
 450 };
 451
 452 &sys_clk {
 453         compatible = "socionext,uniphier-pxs2-clock";
 454 };
 455
 456 &sys_rst {
 457         compatible = "socionext,uniphier-pxs2-reset";
 458 };