2 * Device Tree Source for UniPhier PXs2 SoC
4 * Copyright (C) 2015-2016 Socionext Inc.
5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
7 * SPDX-License-Identifier: GPL-2.0+ X11
10 /include/ "uniphier-common32.dtsi"
13 compatible = "socionext,uniphier-pxs2";
21 compatible = "arm,cortex-a9";
23 enable-method = "psci";
24 next-level-cache = <&l2>;
29 compatible = "arm,cortex-a9";
31 enable-method = "psci";
32 next-level-cache = <&l2>;
37 compatible = "arm,cortex-a9";
39 enable-method = "psci";
40 next-level-cache = <&l2>;
45 compatible = "arm,cortex-a9";
47 enable-method = "psci";
48 next-level-cache = <&l2>;
53 arm_timer_clk: arm_timer_clk {
55 compatible = "fixed-clock";
56 clock-frequency = <50000000>;
61 compatible = "fixed-clock";
62 clock-frequency = <50000000>;
68 l2: l2-cache@500c0000 {
69 compatible = "socionext,uniphier-system-cache";
70 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>;
71 interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>;
73 cache-size = <(1280 * 1024)>;
75 cache-line-size = <128>;
79 port0x: gpio@55000008 {
80 compatible = "socionext,uniphier-gpio";
81 reg = <0x55000008 0x8>;
86 port1x: gpio@55000010 {
87 compatible = "socionext,uniphier-gpio";
88 reg = <0x55000010 0x8>;
93 port2x: gpio@55000018 {
94 compatible = "socionext,uniphier-gpio";
95 reg = <0x55000018 0x8>;
100 port3x: gpio@55000020 {
101 compatible = "socionext,uniphier-gpio";
102 reg = <0x55000020 0x8>;
107 port4: gpio@55000028 {
108 compatible = "socionext,uniphier-gpio";
109 reg = <0x55000028 0x8>;
114 port5x: gpio@55000030 {
115 compatible = "socionext,uniphier-gpio";
116 reg = <0x55000030 0x8>;
121 port6x: gpio@55000038 {
122 compatible = "socionext,uniphier-gpio";
123 reg = <0x55000038 0x8>;
128 port7x: gpio@55000040 {
129 compatible = "socionext,uniphier-gpio";
130 reg = <0x55000040 0x8>;
135 port8x: gpio@55000048 {
136 compatible = "socionext,uniphier-gpio";
137 reg = <0x55000048 0x8>;
142 port9x: gpio@55000050 {
143 compatible = "socionext,uniphier-gpio";
144 reg = <0x55000050 0x8>;
149 port10x: gpio@55000058 {
150 compatible = "socionext,uniphier-gpio";
151 reg = <0x55000058 0x8>;
156 port12x: gpio@55000068 {
157 compatible = "socionext,uniphier-gpio";
158 reg = <0x55000068 0x8>;
163 port13x: gpio@55000070 {
164 compatible = "socionext,uniphier-gpio";
165 reg = <0x55000070 0x8>;
170 port14x: gpio@55000078 {
171 compatible = "socionext,uniphier-gpio";
172 reg = <0x55000078 0x8>;
177 port15x: gpio@55000080 {
178 compatible = "socionext,uniphier-gpio";
179 reg = <0x55000080 0x8>;
184 port16x: gpio@55000088 {
185 compatible = "socionext,uniphier-gpio";
186 reg = <0x55000088 0x8>;
191 port17x: gpio@550000a0 {
192 compatible = "socionext,uniphier-gpio";
193 reg = <0x550000a0 0x8>;
198 port18x: gpio@550000a8 {
199 compatible = "socionext,uniphier-gpio";
200 reg = <0x550000a8 0x8>;
205 port19x: gpio@550000b0 {
206 compatible = "socionext,uniphier-gpio";
207 reg = <0x550000b0 0x8>;
212 port20x: gpio@550000b8 {
213 compatible = "socionext,uniphier-gpio";
214 reg = <0x550000b8 0x8>;
219 port21x: gpio@550000c0 {
220 compatible = "socionext,uniphier-gpio";
221 reg = <0x550000c0 0x8>;
226 port22x: gpio@550000c8 {
227 compatible = "socionext,uniphier-gpio";
228 reg = <0x550000c8 0x8>;
233 port23x: gpio@550000d0 {
234 compatible = "socionext,uniphier-gpio";
235 reg = <0x550000d0 0x8>;
240 port24x: gpio@550000d8 {
241 compatible = "socionext,uniphier-gpio";
242 reg = <0x550000d8 0x8>;
247 port25x: gpio@550000e0 {
248 compatible = "socionext,uniphier-gpio";
249 reg = <0x550000e0 0x8>;
254 port26x: gpio@550000e8 {
255 compatible = "socionext,uniphier-gpio";
256 reg = <0x550000e8 0x8>;
261 port27x: gpio@550000f0 {
262 compatible = "socionext,uniphier-gpio";
263 reg = <0x550000f0 0x8>;
268 port28x: gpio@550000f8 {
269 compatible = "socionext,uniphier-gpio";
270 reg = <0x550000f8 0x8>;
276 compatible = "socionext,uniphier-fi2c";
278 reg = <0x58780000 0x80>;
279 #address-cells = <1>;
281 interrupts = <0 41 4>;
282 pinctrl-names = "default";
283 pinctrl-0 = <&pinctrl_i2c0>;
285 clock-frequency = <100000>;
289 compatible = "socionext,uniphier-fi2c";
291 reg = <0x58781000 0x80>;
292 #address-cells = <1>;
294 interrupts = <0 42 4>;
295 pinctrl-names = "default";
296 pinctrl-0 = <&pinctrl_i2c1>;
298 clock-frequency = <100000>;
302 compatible = "socionext,uniphier-fi2c";
304 reg = <0x58782000 0x80>;
305 #address-cells = <1>;
307 pinctrl-names = "default";
308 pinctrl-0 = <&pinctrl_i2c2>;
309 interrupts = <0 43 4>;
311 clock-frequency = <100000>;
315 compatible = "socionext,uniphier-fi2c";
317 reg = <0x58783000 0x80>;
318 #address-cells = <1>;
320 interrupts = <0 44 4>;
321 pinctrl-names = "default";
322 pinctrl-0 = <&pinctrl_i2c3>;
324 clock-frequency = <100000>;
327 /* chip-internal connection for DMD */
329 compatible = "socionext,uniphier-fi2c";
330 reg = <0x58784000 0x80>;
331 #address-cells = <1>;
333 interrupts = <0 45 4>;
335 clock-frequency = <400000>;
338 /* chip-internal connection for STM */
340 compatible = "socionext,uniphier-fi2c";
341 reg = <0x58785000 0x80>;
342 #address-cells = <1>;
344 interrupts = <0 25 4>;
346 clock-frequency = <400000>;
349 /* chip-internal connection for HDMI */
351 compatible = "socionext,uniphier-fi2c";
352 reg = <0x58786000 0x80>;
353 #address-cells = <1>;
355 interrupts = <0 26 4>;
357 clock-frequency = <400000>;
360 emmc: sdhc@5a000000 {
361 compatible = "socionext,uniphier-sdhc";
363 reg = <0x5a000000 0x800>;
364 interrupts = <0 78 4>;
365 pinctrl-names = "default";
366 pinctrl-0 = <&pinctrl_emmc>;
367 clocks = <&mio_clk 1>;
368 reset-names = "host", "hw-reset";
369 resets = <&mio_rst 1>, <&mio_rst 6>;
375 compatible = "socionext,uniphier-sdhc";
377 reg = <0x5a400000 0x800>;
378 interrupts = <0 76 4>;
379 pinctrl-names = "default", "1.8v";
380 pinctrl-0 = <&pinctrl_sd>;
381 pinctrl-1 = <&pinctrl_sd_1v8>;
382 clocks = <&mio_clk 0>;
383 reset-names = "host";
384 resets = <&mio_rst 0>;
389 compatible = "simple-mfd", "syscon";
390 reg = <0x5fc20000 0x200>;
394 compatible = "socionext,uniphier-xhci", "generic-xhci";
396 reg = <0x65a00000 0x100>;
397 interrupts = <0 134 4>;
398 pinctrl-names = "default";
399 pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
403 compatible = "socionext,uniphier-xhci", "generic-xhci";
405 reg = <0x65c00000 0x100>;
406 interrupts = <0 137 4>;
407 pinctrl-names = "default";
408 pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
413 clock-frequency = <25000000>;
417 clock-frequency = <88900000>;
421 clock-frequency = <88900000>;
425 clock-frequency = <88900000>;
429 clock-frequency = <88900000>;
433 compatible = "socionext,uniphier-pxs2-mio-clock";
437 compatible = "socionext,uniphier-pxs2-mio-reset";
441 compatible = "socionext,uniphier-pxs2-peri-clock";
445 compatible = "socionext,uniphier-pxs2-peri-reset";
449 compatible = "socionext,uniphier-pxs2-pinctrl";
453 compatible = "socionext,uniphier-pxs2-clock";
457 compatible = "socionext,uniphier-pxs2-reset";