2 * Device Tree Source for UniPhier PXs2 SoC
4 * Copyright (C) 2015-2016 Socionext Inc.
5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
7 * SPDX-License-Identifier: GPL-2.0+ X11
10 /include/ "skeleton.dtsi"
13 compatible = "socionext,uniphier-pxs2";
21 compatible = "arm,cortex-a9";
23 clocks = <&sys_clk 32>;
24 enable-method = "psci";
25 next-level-cache = <&l2>;
26 operating-points-v2 = <&cpu_opp>;
31 compatible = "arm,cortex-a9";
33 clocks = <&sys_clk 32>;
34 enable-method = "psci";
35 next-level-cache = <&l2>;
36 operating-points-v2 = <&cpu_opp>;
41 compatible = "arm,cortex-a9";
43 clocks = <&sys_clk 32>;
44 enable-method = "psci";
45 next-level-cache = <&l2>;
46 operating-points-v2 = <&cpu_opp>;
51 compatible = "arm,cortex-a9";
53 clocks = <&sys_clk 32>;
54 enable-method = "psci";
55 next-level-cache = <&l2>;
56 operating-points-v2 = <&cpu_opp>;
61 compatible = "operating-points-v2";
65 opp-hz = /bits/ 64 <100000000>;
66 clock-latency-ns = <300>;
69 opp-hz = /bits/ 64 <150000000>;
70 clock-latency-ns = <300>;
73 opp-hz = /bits/ 64 <200000000>;
74 clock-latency-ns = <300>;
77 opp-hz = /bits/ 64 <300000000>;
78 clock-latency-ns = <300>;
81 opp-hz = /bits/ 64 <400000000>;
82 clock-latency-ns = <300>;
85 opp-hz = /bits/ 64 <600000000>;
86 clock-latency-ns = <300>;
89 opp-hz = /bits/ 64 <800000000>;
90 clock-latency-ns = <300>;
93 opp-hz = /bits/ 64 <1200000000>;
94 clock-latency-ns = <300>;
99 compatible = "arm,psci-0.2";
105 compatible = "fixed-clock";
107 clock-frequency = <25000000>;
110 arm_timer_clk: arm_timer_clk {
112 compatible = "fixed-clock";
113 clock-frequency = <50000000>;
118 compatible = "fixed-clock";
119 clock-frequency = <50000000>;
124 compatible = "simple-bus";
125 #address-cells = <1>;
128 interrupt-parent = <&intc>;
131 l2: l2-cache@500c0000 {
132 compatible = "socionext,uniphier-system-cache";
133 reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
135 interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>;
137 cache-size = <(1280 * 1024)>;
139 cache-line-size = <128>;
143 serial0: serial@54006800 {
144 compatible = "socionext,uniphier-uart";
146 reg = <0x54006800 0x40>;
147 interrupts = <0 33 4>;
148 pinctrl-names = "default";
149 pinctrl-0 = <&pinctrl_uart0>;
150 clocks = <&peri_clk 0>;
151 clock-frequency = <88900000>;
154 serial1: serial@54006900 {
155 compatible = "socionext,uniphier-uart";
157 reg = <0x54006900 0x40>;
158 interrupts = <0 35 4>;
159 pinctrl-names = "default";
160 pinctrl-0 = <&pinctrl_uart1>;
161 clocks = <&peri_clk 1>;
162 clock-frequency = <88900000>;
165 serial2: serial@54006a00 {
166 compatible = "socionext,uniphier-uart";
168 reg = <0x54006a00 0x40>;
169 interrupts = <0 37 4>;
170 pinctrl-names = "default";
171 pinctrl-0 = <&pinctrl_uart2>;
172 clocks = <&peri_clk 2>;
173 clock-frequency = <88900000>;
176 serial3: serial@54006b00 {
177 compatible = "socionext,uniphier-uart";
179 reg = <0x54006b00 0x40>;
180 interrupts = <0 177 4>;
181 pinctrl-names = "default";
182 pinctrl-0 = <&pinctrl_uart3>;
183 clocks = <&peri_clk 3>;
184 clock-frequency = <88900000>;
187 port0x: gpio@55000008 {
188 compatible = "socionext,uniphier-gpio";
189 reg = <0x55000008 0x8>;
194 port1x: gpio@55000010 {
195 compatible = "socionext,uniphier-gpio";
196 reg = <0x55000010 0x8>;
201 port2x: gpio@55000018 {
202 compatible = "socionext,uniphier-gpio";
203 reg = <0x55000018 0x8>;
208 port3x: gpio@55000020 {
209 compatible = "socionext,uniphier-gpio";
210 reg = <0x55000020 0x8>;
215 port4: gpio@55000028 {
216 compatible = "socionext,uniphier-gpio";
217 reg = <0x55000028 0x8>;
222 port5x: gpio@55000030 {
223 compatible = "socionext,uniphier-gpio";
224 reg = <0x55000030 0x8>;
229 port6x: gpio@55000038 {
230 compatible = "socionext,uniphier-gpio";
231 reg = <0x55000038 0x8>;
236 port7x: gpio@55000040 {
237 compatible = "socionext,uniphier-gpio";
238 reg = <0x55000040 0x8>;
243 port8x: gpio@55000048 {
244 compatible = "socionext,uniphier-gpio";
245 reg = <0x55000048 0x8>;
250 port9x: gpio@55000050 {
251 compatible = "socionext,uniphier-gpio";
252 reg = <0x55000050 0x8>;
257 port10x: gpio@55000058 {
258 compatible = "socionext,uniphier-gpio";
259 reg = <0x55000058 0x8>;
264 port12x: gpio@55000068 {
265 compatible = "socionext,uniphier-gpio";
266 reg = <0x55000068 0x8>;
271 port13x: gpio@55000070 {
272 compatible = "socionext,uniphier-gpio";
273 reg = <0x55000070 0x8>;
278 port14x: gpio@55000078 {
279 compatible = "socionext,uniphier-gpio";
280 reg = <0x55000078 0x8>;
285 port15x: gpio@55000080 {
286 compatible = "socionext,uniphier-gpio";
287 reg = <0x55000080 0x8>;
292 port16x: gpio@55000088 {
293 compatible = "socionext,uniphier-gpio";
294 reg = <0x55000088 0x8>;
299 port17x: gpio@550000a0 {
300 compatible = "socionext,uniphier-gpio";
301 reg = <0x550000a0 0x8>;
306 port18x: gpio@550000a8 {
307 compatible = "socionext,uniphier-gpio";
308 reg = <0x550000a8 0x8>;
313 port19x: gpio@550000b0 {
314 compatible = "socionext,uniphier-gpio";
315 reg = <0x550000b0 0x8>;
320 port20x: gpio@550000b8 {
321 compatible = "socionext,uniphier-gpio";
322 reg = <0x550000b8 0x8>;
327 port21x: gpio@550000c0 {
328 compatible = "socionext,uniphier-gpio";
329 reg = <0x550000c0 0x8>;
334 port22x: gpio@550000c8 {
335 compatible = "socionext,uniphier-gpio";
336 reg = <0x550000c8 0x8>;
341 port23x: gpio@550000d0 {
342 compatible = "socionext,uniphier-gpio";
343 reg = <0x550000d0 0x8>;
348 port24x: gpio@550000d8 {
349 compatible = "socionext,uniphier-gpio";
350 reg = <0x550000d8 0x8>;
355 port25x: gpio@550000e0 {
356 compatible = "socionext,uniphier-gpio";
357 reg = <0x550000e0 0x8>;
362 port26x: gpio@550000e8 {
363 compatible = "socionext,uniphier-gpio";
364 reg = <0x550000e8 0x8>;
369 port27x: gpio@550000f0 {
370 compatible = "socionext,uniphier-gpio";
371 reg = <0x550000f0 0x8>;
376 port28x: gpio@550000f8 {
377 compatible = "socionext,uniphier-gpio";
378 reg = <0x550000f8 0x8>;
384 compatible = "socionext,uniphier-fi2c";
386 reg = <0x58780000 0x80>;
387 #address-cells = <1>;
389 interrupts = <0 41 4>;
390 pinctrl-names = "default";
391 pinctrl-0 = <&pinctrl_i2c0>;
393 clock-frequency = <100000>;
397 compatible = "socionext,uniphier-fi2c";
399 reg = <0x58781000 0x80>;
400 #address-cells = <1>;
402 interrupts = <0 42 4>;
403 pinctrl-names = "default";
404 pinctrl-0 = <&pinctrl_i2c1>;
406 clock-frequency = <100000>;
410 compatible = "socionext,uniphier-fi2c";
412 reg = <0x58782000 0x80>;
413 #address-cells = <1>;
415 interrupts = <0 43 4>;
416 pinctrl-names = "default";
417 pinctrl-0 = <&pinctrl_i2c2>;
419 clock-frequency = <100000>;
423 compatible = "socionext,uniphier-fi2c";
425 reg = <0x58783000 0x80>;
426 #address-cells = <1>;
428 interrupts = <0 44 4>;
429 pinctrl-names = "default";
430 pinctrl-0 = <&pinctrl_i2c3>;
432 clock-frequency = <100000>;
435 /* chip-internal connection for DMD */
437 compatible = "socionext,uniphier-fi2c";
438 reg = <0x58784000 0x80>;
439 #address-cells = <1>;
441 interrupts = <0 45 4>;
443 clock-frequency = <400000>;
446 /* chip-internal connection for STM */
448 compatible = "socionext,uniphier-fi2c";
449 reg = <0x58785000 0x80>;
450 #address-cells = <1>;
452 interrupts = <0 25 4>;
454 clock-frequency = <400000>;
457 /* chip-internal connection for HDMI */
459 compatible = "socionext,uniphier-fi2c";
460 reg = <0x58786000 0x80>;
461 #address-cells = <1>;
463 interrupts = <0 26 4>;
465 clock-frequency = <400000>;
468 system_bus: system-bus@58c00000 {
469 compatible = "socionext,uniphier-system-bus";
471 reg = <0x58c00000 0x400>;
472 #address-cells = <2>;
474 pinctrl-names = "default";
475 pinctrl-0 = <&pinctrl_system_bus>;
479 compatible = "socionext,uniphier-smpctrl";
480 reg = <0x59801000 0x400>;
484 compatible = "socionext,uniphier-pxs2-sdctrl",
485 "simple-mfd", "syscon";
486 reg = <0x59810000 0x800>;
490 compatible = "socionext,uniphier-pxs2-sd-clock";
495 compatible = "socionext,uniphier-pxs2-sd-reset";
501 compatible = "socionext,uniphier-pxs2-perictrl",
502 "simple-mfd", "syscon";
503 reg = <0x59820000 0x200>;
506 compatible = "socionext,uniphier-pxs2-peri-clock";
511 compatible = "socionext,uniphier-pxs2-peri-reset";
516 emmc: sdhc@5a000000 {
517 compatible = "socionext,uniphier-sdhc";
519 reg = <0x5a000000 0x800>;
520 interrupts = <0 78 4>;
521 pinctrl-names = "default";
522 pinctrl-0 = <&pinctrl_emmc>;
523 clocks = <&sd_clk 1>;
524 reset-names = "host";
525 resets = <&sd_rst 1>;
534 compatible = "socionext,uniphier-sdhc";
536 reg = <0x5a400000 0x800>;
537 interrupts = <0 76 4>;
538 pinctrl-names = "default", "1.8v";
539 pinctrl-0 = <&pinctrl_sd>;
540 pinctrl-1 = <&pinctrl_sd_1v8>;
541 clocks = <&sd_clk 0>;
542 reset-names = "host";
543 resets = <&sd_rst 0>;
552 compatible = "socionext,uniphier-pxs2-soc-glue",
553 "simple-mfd", "syscon";
554 reg = <0x5f800000 0x2000>;
558 compatible = "socionext,uniphier-pxs2-pinctrl";
564 compatible = "simple-mfd", "syscon";
565 reg = <0x5fc20000 0x200>;
569 compatible = "arm,cortex-a9-global-timer";
570 reg = <0x60000200 0x20>;
571 interrupts = <1 11 0xf04>;
572 clocks = <&arm_timer_clk>;
576 compatible = "arm,cortex-a9-twd-timer";
577 reg = <0x60000600 0x20>;
578 interrupts = <1 13 0xf04>;
579 clocks = <&arm_timer_clk>;
582 intc: interrupt-controller@60001000 {
583 compatible = "arm,cortex-a9-gic";
584 reg = <0x60001000 0x1000>,
586 #interrupt-cells = <3>;
587 interrupt-controller;
591 compatible = "socionext,uniphier-pxs2-sysctrl",
592 "simple-mfd", "syscon";
593 reg = <0x61840000 0x4000>;
596 compatible = "socionext,uniphier-pxs2-clock";
601 compatible = "socionext,uniphier-pxs2-reset";
607 compatible = "socionext,uniphier-pxs2-dwc3";
609 reg = <0x65b00000 0x1000>;
610 #address-cells = <1>;
613 pinctrl-names = "default";
614 pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
616 compatible = "snps,dwc3";
617 reg = <0x65a00000 0x10000>;
618 interrupts = <0 134 4>;
624 compatible = "socionext,uniphier-pxs2-dwc3";
626 reg = <0x65d00000 0x1000>;
627 #address-cells = <1>;
630 pinctrl-names = "default";
631 pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
633 compatible = "snps,dwc3";
634 reg = <0x65c00000 0x10000>;
635 interrupts = <0 137 4>;
640 nand: nand@68000000 {
641 compatible = "socionext,denali-nand-v5b";
643 reg-names = "nand_data", "denali_reg";
644 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
645 interrupts = <0 65 4>;
646 pinctrl-names = "default";
647 pinctrl-0 = <&pinctrl_nand>;
648 clocks = <&sys_clk 2>;
649 nand-ecc-strength = <8>;
654 /include/ "uniphier-pinctrl.dtsi"