1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Device Tree Source for UniPhier PXs2 SoC
5 // Copyright (C) 2015-2016 Socionext Inc.
6 // Author: Masahiro Yamada <yamada.masahiro@socionext.com>
8 #include <dt-bindings/gpio/uniphier-gpio.h>
9 #include <dt-bindings/thermal/thermal.h>
12 compatible = "socionext,uniphier-pxs2";
22 compatible = "arm,cortex-a9";
24 clocks = <&sys_clk 32>;
25 enable-method = "psci";
26 next-level-cache = <&l2>;
27 operating-points-v2 = <&cpu_opp>;
33 compatible = "arm,cortex-a9";
35 clocks = <&sys_clk 32>;
36 enable-method = "psci";
37 next-level-cache = <&l2>;
38 operating-points-v2 = <&cpu_opp>;
43 compatible = "arm,cortex-a9";
45 clocks = <&sys_clk 32>;
46 enable-method = "psci";
47 next-level-cache = <&l2>;
48 operating-points-v2 = <&cpu_opp>;
53 compatible = "arm,cortex-a9";
55 clocks = <&sys_clk 32>;
56 enable-method = "psci";
57 next-level-cache = <&l2>;
58 operating-points-v2 = <&cpu_opp>;
63 compatible = "operating-points-v2";
67 opp-hz = /bits/ 64 <100000000>;
68 clock-latency-ns = <300>;
71 opp-hz = /bits/ 64 <150000000>;
72 clock-latency-ns = <300>;
75 opp-hz = /bits/ 64 <200000000>;
76 clock-latency-ns = <300>;
79 opp-hz = /bits/ 64 <300000000>;
80 clock-latency-ns = <300>;
83 opp-hz = /bits/ 64 <400000000>;
84 clock-latency-ns = <300>;
87 opp-hz = /bits/ 64 <600000000>;
88 clock-latency-ns = <300>;
91 opp-hz = /bits/ 64 <800000000>;
92 clock-latency-ns = <300>;
95 opp-hz = /bits/ 64 <1200000000>;
96 clock-latency-ns = <300>;
101 compatible = "arm,psci-0.2";
107 compatible = "fixed-clock";
109 clock-frequency = <25000000>;
112 arm_timer_clk: arm-timer {
114 compatible = "fixed-clock";
115 clock-frequency = <50000000>;
121 polling-delay-passive = <250>; /* 250ms */
122 polling-delay = <1000>; /* 1000ms */
123 thermal-sensors = <&pvtctl>;
127 temperature = <95000>; /* 95C */
131 cpu_alert: cpu-alert {
132 temperature = <85000>; /* 85C */
141 cooling-device = <&cpu0
142 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
149 compatible = "simple-bus";
150 #address-cells = <1>;
153 interrupt-parent = <&intc>;
155 l2: l2-cache@500c0000 {
156 compatible = "socionext,uniphier-system-cache";
157 reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
159 interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>;
161 cache-size = <(1280 * 1024)>;
163 cache-line-size = <128>;
167 serial0: serial@54006800 {
168 compatible = "socionext,uniphier-uart";
170 reg = <0x54006800 0x40>;
171 interrupts = <0 33 4>;
172 pinctrl-names = "default";
173 pinctrl-0 = <&pinctrl_uart0>;
174 clocks = <&peri_clk 0>;
175 resets = <&peri_rst 0>;
178 serial1: serial@54006900 {
179 compatible = "socionext,uniphier-uart";
181 reg = <0x54006900 0x40>;
182 interrupts = <0 35 4>;
183 pinctrl-names = "default";
184 pinctrl-0 = <&pinctrl_uart1>;
185 clocks = <&peri_clk 1>;
186 resets = <&peri_rst 1>;
189 serial2: serial@54006a00 {
190 compatible = "socionext,uniphier-uart";
192 reg = <0x54006a00 0x40>;
193 interrupts = <0 37 4>;
194 pinctrl-names = "default";
195 pinctrl-0 = <&pinctrl_uart2>;
196 clocks = <&peri_clk 2>;
197 resets = <&peri_rst 2>;
200 serial3: serial@54006b00 {
201 compatible = "socionext,uniphier-uart";
203 reg = <0x54006b00 0x40>;
204 interrupts = <0 177 4>;
205 pinctrl-names = "default";
206 pinctrl-0 = <&pinctrl_uart3>;
207 clocks = <&peri_clk 3>;
208 resets = <&peri_rst 3>;
211 gpio: gpio@55000000 {
212 compatible = "socionext,uniphier-gpio";
213 reg = <0x55000000 0x200>;
214 interrupt-parent = <&aidet>;
215 interrupt-controller;
216 #interrupt-cells = <2>;
219 gpio-ranges = <&pinctrl 0 0 0>,
221 gpio-ranges-group-names = "gpio_range0",
224 socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
229 compatible = "socionext,uniphier-pxs2-aio";
230 reg = <0x56000000 0x80000>;
231 interrupts = <0 144 4>;
232 pinctrl-names = "default";
233 pinctrl-0 = <&pinctrl_ain1>,
241 clocks = <&sys_clk 40>;
243 resets = <&sys_rst 40>;
244 #sound-dai-cells = <1>;
245 socionext,syscon = <&soc_glue>;
262 spdif_port0: port@3 {
263 spdif_hiecout1: endpoint {
267 spdif_port1: port@4 {
268 spdif_iecout1: endpoint {
272 comp_spdif_port0: port@5 {
273 comp_spdif_hiecout1: endpoint {
277 comp_spdif_port1: port@6 {
278 comp_spdif_iecout1: endpoint {
284 compatible = "socionext,uniphier-fi2c";
286 reg = <0x58780000 0x80>;
287 #address-cells = <1>;
289 interrupts = <0 41 4>;
290 pinctrl-names = "default";
291 pinctrl-0 = <&pinctrl_i2c0>;
292 clocks = <&peri_clk 4>;
293 resets = <&peri_rst 4>;
294 clock-frequency = <100000>;
298 compatible = "socionext,uniphier-fi2c";
300 reg = <0x58781000 0x80>;
301 #address-cells = <1>;
303 interrupts = <0 42 4>;
304 pinctrl-names = "default";
305 pinctrl-0 = <&pinctrl_i2c1>;
306 clocks = <&peri_clk 5>;
307 resets = <&peri_rst 5>;
308 clock-frequency = <100000>;
312 compatible = "socionext,uniphier-fi2c";
314 reg = <0x58782000 0x80>;
315 #address-cells = <1>;
317 interrupts = <0 43 4>;
318 pinctrl-names = "default";
319 pinctrl-0 = <&pinctrl_i2c2>;
320 clocks = <&peri_clk 6>;
321 resets = <&peri_rst 6>;
322 clock-frequency = <100000>;
326 compatible = "socionext,uniphier-fi2c";
328 reg = <0x58783000 0x80>;
329 #address-cells = <1>;
331 interrupts = <0 44 4>;
332 pinctrl-names = "default";
333 pinctrl-0 = <&pinctrl_i2c3>;
334 clocks = <&peri_clk 7>;
335 resets = <&peri_rst 7>;
336 clock-frequency = <100000>;
339 /* chip-internal connection for DMD */
341 compatible = "socionext,uniphier-fi2c";
342 reg = <0x58784000 0x80>;
343 #address-cells = <1>;
345 interrupts = <0 45 4>;
346 clocks = <&peri_clk 8>;
347 resets = <&peri_rst 8>;
348 clock-frequency = <400000>;
351 /* chip-internal connection for STM */
353 compatible = "socionext,uniphier-fi2c";
354 reg = <0x58785000 0x80>;
355 #address-cells = <1>;
357 interrupts = <0 25 4>;
358 clocks = <&peri_clk 9>;
359 resets = <&peri_rst 9>;
360 clock-frequency = <400000>;
363 /* chip-internal connection for HDMI */
365 compatible = "socionext,uniphier-fi2c";
366 reg = <0x58786000 0x80>;
367 #address-cells = <1>;
369 interrupts = <0 26 4>;
370 clocks = <&peri_clk 10>;
371 resets = <&peri_rst 10>;
372 clock-frequency = <400000>;
375 system_bus: system-bus@58c00000 {
376 compatible = "socionext,uniphier-system-bus";
378 reg = <0x58c00000 0x400>;
379 #address-cells = <2>;
381 pinctrl-names = "default";
382 pinctrl-0 = <&pinctrl_system_bus>;
386 compatible = "socionext,uniphier-smpctrl";
387 reg = <0x59801000 0x400>;
391 compatible = "socionext,uniphier-pxs2-sdctrl",
392 "simple-mfd", "syscon";
393 reg = <0x59810000 0x400>;
396 compatible = "socionext,uniphier-pxs2-sd-clock";
401 compatible = "socionext,uniphier-pxs2-sd-reset";
407 compatible = "socionext,uniphier-pxs2-perictrl",
408 "simple-mfd", "syscon";
409 reg = <0x59820000 0x200>;
412 compatible = "socionext,uniphier-pxs2-peri-clock";
417 compatible = "socionext,uniphier-pxs2-peri-reset";
422 emmc: sdhc@5a000000 {
423 compatible = "socionext,uniphier-sdhc";
425 reg = <0x5a000000 0x800>;
426 interrupts = <0 78 4>;
427 pinctrl-names = "default";
428 pinctrl-0 = <&pinctrl_emmc>;
429 clocks = <&sd_clk 1>;
430 reset-names = "host";
431 resets = <&sd_rst 1>;
440 compatible = "socionext,uniphier-sdhc";
442 reg = <0x5a400000 0x800>;
443 interrupts = <0 76 4>;
444 pinctrl-names = "default", "1.8v";
445 pinctrl-0 = <&pinctrl_sd>;
446 pinctrl-1 = <&pinctrl_sd_1v8>;
447 clocks = <&sd_clk 0>;
448 reset-names = "host";
449 resets = <&sd_rst 0>;
457 soc_glue: soc-glue@5f800000 {
458 compatible = "socionext,uniphier-pxs2-soc-glue",
459 "simple-mfd", "syscon";
460 reg = <0x5f800000 0x2000>;
463 compatible = "socionext,uniphier-pxs2-pinctrl";
468 compatible = "socionext,uniphier-pxs2-soc-glue-debug",
470 #address-cells = <1>;
472 ranges = <0 0x5f900000 0x2000>;
475 compatible = "socionext,uniphier-efuse";
480 compatible = "socionext,uniphier-efuse";
485 aidet: aidet@5fc20000 {
486 compatible = "socionext,uniphier-pxs2-aidet";
487 reg = <0x5fc20000 0x200>;
488 interrupt-controller;
489 #interrupt-cells = <2>;
493 compatible = "arm,cortex-a9-global-timer";
494 reg = <0x60000200 0x20>;
495 interrupts = <1 11 0xf04>;
496 clocks = <&arm_timer_clk>;
500 compatible = "arm,cortex-a9-twd-timer";
501 reg = <0x60000600 0x20>;
502 interrupts = <1 13 0xf04>;
503 clocks = <&arm_timer_clk>;
506 intc: interrupt-controller@60001000 {
507 compatible = "arm,cortex-a9-gic";
508 reg = <0x60001000 0x1000>,
510 #interrupt-cells = <3>;
511 interrupt-controller;
515 compatible = "socionext,uniphier-pxs2-sysctrl",
516 "simple-mfd", "syscon";
517 reg = <0x61840000 0x10000>;
520 compatible = "socionext,uniphier-pxs2-clock";
525 compatible = "socionext,uniphier-pxs2-reset";
530 compatible = "socionext,uniphier-pxs2-thermal";
531 interrupts = <0 3 4>;
532 #thermal-sensor-cells = <0>;
533 socionext,tmod-calibration = <0x0f86 0x6844>;
537 eth: ethernet@65000000 {
538 compatible = "socionext,uniphier-pxs2-ave4";
540 reg = <0x65000000 0x8500>;
541 interrupts = <0 66 4>;
542 pinctrl-names = "default";
543 pinctrl-0 = <&pinctrl_ether_rgmii>;
544 clock-names = "ether";
545 clocks = <&sys_clk 6>;
546 reset-names = "ether";
547 resets = <&sys_rst 6>;
549 local-mac-address = [00 00 00 00 00 00];
550 socionext,syscon-phy-mode = <&soc_glue 0>;
553 #address-cells = <1>;
559 compatible = "socionext,uniphier-pxs2-dwc3";
561 reg = <0x65b00000 0x1000>;
562 #address-cells = <1>;
565 pinctrl-names = "default";
566 pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
568 compatible = "snps,dwc3";
569 reg = <0x65a00000 0x10000>;
570 interrupts = <0 134 4>;
577 compatible = "socionext,uniphier-pxs2-dwc3";
579 reg = <0x65d00000 0x1000>;
580 #address-cells = <1>;
583 pinctrl-names = "default";
584 pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
586 compatible = "snps,dwc3";
587 reg = <0x65c00000 0x10000>;
588 interrupts = <0 137 4>;
594 nand: nand@68000000 {
595 compatible = "socionext,uniphier-denali-nand-v5b";
597 reg-names = "nand_data", "denali_reg";
598 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
599 interrupts = <0 65 4>;
600 pinctrl-names = "default";
601 pinctrl-0 = <&pinctrl_nand2cs>;
602 clocks = <&sys_clk 2>;
603 resets = <&sys_rst 2>;
608 #include "uniphier-pinctrl.dtsi"