2 * Device Tree Source for UniPhier PXs3 SoC
4 * Copyright (C) 2017 Socionext Inc.
5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
7 * SPDX-License-Identifier: GPL-2.0+ X11
10 /memreserve/ 0x80000000 0x00080000;
13 compatible = "socionext,uniphier-pxs3";
16 interrupt-parent = <&gic>;
41 compatible = "arm,cortex-a53", "arm,armv8";
43 enable-method = "psci";
48 compatible = "arm,cortex-a53", "arm,armv8";
50 enable-method = "psci";
55 compatible = "arm,cortex-a53", "arm,armv8";
57 enable-method = "psci";
62 compatible = "arm,cortex-a53", "arm,armv8";
64 enable-method = "psci";
69 compatible = "arm,psci-1.0";
75 compatible = "fixed-clock";
77 clock-frequency = <25000000>;
82 compatible = "arm,armv8-timer";
83 interrupts = <1 13 4>,
90 compatible = "simple-bus";
93 ranges = <0 0 0 0xffffffff>;
95 serial0: serial@54006800 {
96 compatible = "socionext,uniphier-uart";
98 reg = <0x54006800 0x40>;
99 interrupts = <0 33 4>;
100 pinctrl-names = "default";
101 pinctrl-0 = <&pinctrl_uart0>;
102 clocks = <&peri_clk 0>;
103 clock-frequency = <58820000>;
106 serial1: serial@54006900 {
107 compatible = "socionext,uniphier-uart";
109 reg = <0x54006900 0x40>;
110 interrupts = <0 35 4>;
111 pinctrl-names = "default";
112 pinctrl-0 = <&pinctrl_uart1>;
113 clocks = <&peri_clk 1>;
114 clock-frequency = <58820000>;
117 serial2: serial@54006a00 {
118 compatible = "socionext,uniphier-uart";
120 reg = <0x54006a00 0x40>;
121 interrupts = <0 37 4>;
122 pinctrl-names = "default";
123 pinctrl-0 = <&pinctrl_uart2>;
124 clocks = <&peri_clk 2>;
125 clock-frequency = <58820000>;
128 serial3: serial@54006b00 {
129 compatible = "socionext,uniphier-uart";
131 reg = <0x54006b00 0x40>;
132 interrupts = <0 177 4>;
133 pinctrl-names = "default";
134 pinctrl-0 = <&pinctrl_uart3>;
135 clocks = <&peri_clk 3>;
136 clock-frequency = <58820000>;
140 compatible = "socionext,uniphier-fi2c";
142 reg = <0x58780000 0x80>;
143 #address-cells = <1>;
145 interrupts = <0 41 4>;
146 pinctrl-names = "default";
147 pinctrl-0 = <&pinctrl_i2c0>;
148 clocks = <&peri_clk 4>;
149 clock-frequency = <100000>;
153 compatible = "socionext,uniphier-fi2c";
155 reg = <0x58781000 0x80>;
156 #address-cells = <1>;
158 interrupts = <0 42 4>;
159 pinctrl-names = "default";
160 pinctrl-0 = <&pinctrl_i2c1>;
161 clocks = <&peri_clk 5>;
162 clock-frequency = <100000>;
166 compatible = "socionext,uniphier-fi2c";
168 reg = <0x58782000 0x80>;
169 #address-cells = <1>;
171 interrupts = <0 43 4>;
172 clocks = <&peri_clk 6>;
173 clock-frequency = <100000>;
177 compatible = "socionext,uniphier-fi2c";
179 reg = <0x58783000 0x80>;
180 #address-cells = <1>;
182 interrupts = <0 44 4>;
183 pinctrl-names = "default";
184 pinctrl-0 = <&pinctrl_i2c3>;
185 clocks = <&peri_clk 7>;
186 clock-frequency = <100000>;
189 /* chip-internal connection for HDMI */
191 compatible = "socionext,uniphier-fi2c";
192 reg = <0x58786000 0x80>;
193 #address-cells = <1>;
195 interrupts = <0 26 4>;
196 clocks = <&peri_clk 10>;
197 clock-frequency = <400000>;
200 system_bus: system-bus@58c00000 {
201 compatible = "socionext,uniphier-system-bus";
203 reg = <0x58c00000 0x400>;
204 #address-cells = <2>;
206 pinctrl-names = "default";
207 pinctrl-0 = <&pinctrl_system_bus>;
211 compatible = "socionext,uniphier-smpctrl";
212 reg = <0x59801000 0x400>;
216 compatible = "socionext,uniphier-pxs3-sdctrl",
217 "simple-mfd", "syscon";
218 reg = <0x59810000 0x800>;
221 compatible = "socionext,uniphier-pxs3-sd-clock";
226 compatible = "socionext,uniphier-pxs3-sd-reset";
232 compatible = "socionext,uniphier-pxs3-perictrl",
233 "simple-mfd", "syscon";
234 reg = <0x59820000 0x200>;
237 compatible = "socionext,uniphier-pxs3-peri-clock";
242 compatible = "socionext,uniphier-pxs3-peri-reset";
247 emmc: sdhc@5a000000 {
248 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
250 reg = <0x5a000000 0x400>;
251 interrupts = <0 78 4>;
252 pinctrl-names = "default";
253 pinctrl-0 = <&pinctrl_emmc_1v8>;
254 clocks = <&sys_clk 4>;
261 compatible = "socionext,uniphier-sdhc";
263 reg = <0x5a400000 0x800>;
264 interrupts = <0 76 4>;
265 pinctrl-names = "default";
266 pinctrl-0 = <&pinctrl_sd>;
267 clocks = <&sd_clk 0>;
268 reset-names = "host";
269 resets = <&sd_rst 0>;
275 compatible = "socionext,uniphier-pxs3-soc-glue",
276 "simple-mfd", "syscon";
277 reg = <0x5f800000 0x2000>;
280 compatible = "socionext,uniphier-pxs3-pinctrl";
285 compatible = "simple-mfd", "syscon";
286 reg = <0x5fc20000 0x200>;
289 gic: interrupt-controller@5fe00000 {
290 compatible = "arm,gic-v3";
291 reg = <0x5fe00000 0x10000>, /* GICD */
292 <0x5fe80000 0x80000>; /* GICR */
293 interrupt-controller;
294 #interrupt-cells = <3>;
295 interrupts = <1 9 4>;
299 compatible = "socionext,uniphier-pxs3-sysctrl",
300 "simple-mfd", "syscon";
301 reg = <0x61840000 0x10000>;
304 compatible = "socionext,uniphier-pxs3-clock";
309 compatible = "socionext,uniphier-pxs3-reset";
314 nand: nand@68000000 {
315 compatible = "socionext,denali-nand-v5b";
317 reg-names = "nand_data", "denali_reg";
318 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
319 interrupts = <0 65 4>;
320 pinctrl-names = "default";
321 pinctrl-0 = <&pinctrl_nand>;
322 clocks = <&sys_clk 2>;
323 nand-ecc-strength = <8>;
328 /include/ "uniphier-pinctrl.dtsi"