git.sur5r.net Git - u-boot/blob - arch/arm/dts/uniphier-pxs3.dtsi

   1 /*
   2  * Device Tree Source for UniPhier PXs3 SoC
   3  *
   4  * Copyright (C) 2017 Socionext Inc.
   5  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
   6  *
   7  * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   8  */
   9
  10 /memreserve/ 0x80000000 0x02000000;
  11
  12 / {
  13         compatible = "socionext,uniphier-pxs3";
  14         #address-cells = <2>;
  15         #size-cells = <2>;
  16         interrupt-parent = <&gic>;
  17
  18         cpus {
  19                 #address-cells = <2>;
  20                 #size-cells = <0>;
  21
  22                 cpu-map {
  23                         cluster0 {
  24                                 core0 {
  25                                         cpu = <&cpu0>;
  26                                 };
  27                                 core1 {
  28                                         cpu = <&cpu1>;
  29                                 };
  30                                 core2 {
  31                                         cpu = <&cpu2>;
  32                                 };
  33                                 core3 {
  34                                         cpu = <&cpu3>;
  35                                 };
  36                         };
  37                 };
  38
  39                 cpu0: cpu@0 {
  40                         device_type = "cpu";
  41                         compatible = "arm,cortex-a53", "arm,armv8";
  42                         reg = <0 0x000>;
  43                         clocks = <&sys_clk 33>;
  44                         enable-method = "psci";
  45                         operating-points-v2 = <&cluster0_opp>;
  46                 };
  47
  48                 cpu1: cpu@1 {
  49                         device_type = "cpu";
  50                         compatible = "arm,cortex-a53", "arm,armv8";
  51                         reg = <0 0x001>;
  52                         clocks = <&sys_clk 33>;
  53                         enable-method = "psci";
  54                         operating-points-v2 = <&cluster0_opp>;
  55                 };
  56
  57                 cpu2: cpu@2 {
  58                         device_type = "cpu";
  59                         compatible = "arm,cortex-a53", "arm,armv8";
  60                         reg = <0 0x002>;
  61                         clocks = <&sys_clk 33>;
  62                         enable-method = "psci";
  63                         operating-points-v2 = <&cluster0_opp>;
  64                 };
  65
  66                 cpu3: cpu@3 {
  67                         device_type = "cpu";
  68                         compatible = "arm,cortex-a53", "arm,armv8";
  69                         reg = <0 0x003>;
  70                         clocks = <&sys_clk 33>;
  71                         enable-method = "psci";
  72                         operating-points-v2 = <&cluster0_opp>;
  73                 };
  74         };
  75
  76         cluster0_opp: opp_table {
  77                 compatible = "operating-points-v2";
  78                 opp-shared;
  79
  80                 opp-250000000 {
  81                         opp-hz = /bits/ 64 <250000000>;
  82                         clock-latency-ns = <300>;
  83                 };
  84                 opp-325000000 {
  85                         opp-hz = /bits/ 64 <325000000>;
  86                         clock-latency-ns = <300>;
  87                 };
  88                 opp-500000000 {
  89                         opp-hz = /bits/ 64 <500000000>;
  90                         clock-latency-ns = <300>;
  91                 };
  92                 opp-650000000 {
  93                         opp-hz = /bits/ 64 <650000000>;
  94                         clock-latency-ns = <300>;
  95                 };
  96                 opp-666667000 {
  97                         opp-hz = /bits/ 64 <666667000>;
  98                         clock-latency-ns = <300>;
  99                 };
 100                 opp-866667000 {
 101                         opp-hz = /bits/ 64 <866667000>;
 102                         clock-latency-ns = <300>;
 103                 };
 104                 opp-1000000000 {
 105                         opp-hz = /bits/ 64 <1000000000>;
 106                         clock-latency-ns = <300>;
 107                 };
 108                 opp-1300000000 {
 109                         opp-hz = /bits/ 64 <1300000000>;
 110                         clock-latency-ns = <300>;
 111                 };
 112         };
 113
 114         psci {
 115                 compatible = "arm,psci-1.0";
 116                 method = "smc";
 117         };
 118
 119         clocks {
 120                 refclk: ref {
 121                         compatible = "fixed-clock";
 122                         #clock-cells = <0>;
 123                         clock-frequency = <25000000>;
 124                 };
 125         };
 126
 127         timer {
 128                 compatible = "arm,armv8-timer";
 129                 interrupts = <1 13 4>,
 130                              <1 14 4>,
 131                              <1 11 4>,
 132                              <1 10 4>;
 133         };
 134
 135         soc@0 {
 136                 compatible = "simple-bus";
 137                 #address-cells = <1>;
 138                 #size-cells = <1>;
 139                 ranges = <0 0 0 0xffffffff>;
 140
 141                 serial0: serial@54006800 {
 142                         compatible = "socionext,uniphier-uart";
 143                         status = "disabled";
 144                         reg = <0x54006800 0x40>;
 145                         interrupts = <0 33 4>;
 146                         pinctrl-names = "default";
 147                         pinctrl-0 = <&pinctrl_uart0>;
 148                         clocks = <&peri_clk 0>;
 149                         clock-frequency = <58820000>;
 150                 };
 151
 152                 serial1: serial@54006900 {
 153                         compatible = "socionext,uniphier-uart";
 154                         status = "disabled";
 155                         reg = <0x54006900 0x40>;
 156                         interrupts = <0 35 4>;
 157                         pinctrl-names = "default";
 158                         pinctrl-0 = <&pinctrl_uart1>;
 159                         clocks = <&peri_clk 1>;
 160                         clock-frequency = <58820000>;
 161                 };
 162
 163                 serial2: serial@54006a00 {
 164                         compatible = "socionext,uniphier-uart";
 165                         status = "disabled";
 166                         reg = <0x54006a00 0x40>;
 167                         interrupts = <0 37 4>;
 168                         pinctrl-names = "default";
 169                         pinctrl-0 = <&pinctrl_uart2>;
 170                         clocks = <&peri_clk 2>;
 171                         clock-frequency = <58820000>;
 172                 };
 173
 174                 serial3: serial@54006b00 {
 175                         compatible = "socionext,uniphier-uart";
 176                         status = "disabled";
 177                         reg = <0x54006b00 0x40>;
 178                         interrupts = <0 177 4>;
 179                         pinctrl-names = "default";
 180                         pinctrl-0 = <&pinctrl_uart3>;
 181                         clocks = <&peri_clk 3>;
 182                         clock-frequency = <58820000>;
 183                 };
 184
 185                 gpio: gpio@55000000 {
 186                         compatible = "socionext,uniphier-gpio";
 187                         reg = <0x55000000 0x200>;
 188                         interrupt-parent = <&aidet>;
 189                         interrupt-controller;
 190                         #interrupt-cells = <2>;
 191                         gpio-controller;
 192                         #gpio-cells = <2>;
 193                         gpio-ranges = <&pinctrl 0 0 0>,
 194                                       <&pinctrl 96 0 0>,
 195                                       <&pinctrl 160 0 0>;
 196                         gpio-ranges-group-names = "gpio_range0",
 197                                                   "gpio_range1",
 198                                                   "gpio_range2";
 199                         ngpios = <286>;
 200                 };
 201
 202                 i2c0: i2c@58780000 {
 203                         compatible = "socionext,uniphier-fi2c";
 204                         status = "disabled";
 205                         reg = <0x58780000 0x80>;
 206                         #address-cells = <1>;
 207                         #size-cells = <0>;
 208                         interrupts = <0 41 4>;
 209                         pinctrl-names = "default";
 210                         pinctrl-0 = <&pinctrl_i2c0>;
 211                         clocks = <&peri_clk 4>;
 212                         clock-frequency = <100000>;
 213                 };
 214
 215                 i2c1: i2c@58781000 {
 216                         compatible = "socionext,uniphier-fi2c";
 217                         status = "disabled";
 218                         reg = <0x58781000 0x80>;
 219                         #address-cells = <1>;
 220                         #size-cells = <0>;
 221                         interrupts = <0 42 4>;
 222                         pinctrl-names = "default";
 223                         pinctrl-0 = <&pinctrl_i2c1>;
 224                         clocks = <&peri_clk 5>;
 225                         clock-frequency = <100000>;
 226                 };
 227
 228                 i2c2: i2c@58782000 {
 229                         compatible = "socionext,uniphier-fi2c";
 230                         status = "disabled";
 231                         reg = <0x58782000 0x80>;
 232                         #address-cells = <1>;
 233                         #size-cells = <0>;
 234                         interrupts = <0 43 4>;
 235                         pinctrl-names = "default";
 236                         pinctrl-0 = <&pinctrl_i2c2>;
 237                         clocks = <&peri_clk 6>;
 238                         clock-frequency = <100000>;
 239                 };
 240
 241                 i2c3: i2c@58783000 {
 242                         compatible = "socionext,uniphier-fi2c";
 243                         status = "disabled";
 244                         reg = <0x58783000 0x80>;
 245                         #address-cells = <1>;
 246                         #size-cells = <0>;
 247                         interrupts = <0 44 4>;
 248                         pinctrl-names = "default";
 249                         pinctrl-0 = <&pinctrl_i2c3>;
 250                         clocks = <&peri_clk 7>;
 251                         clock-frequency = <100000>;
 252                 };
 253
 254                 /* chip-internal connection for HDMI */
 255                 i2c6: i2c@58786000 {
 256                         compatible = "socionext,uniphier-fi2c";
 257                         reg = <0x58786000 0x80>;
 258                         #address-cells = <1>;
 259                         #size-cells = <0>;
 260                         interrupts = <0 26 4>;
 261                         clocks = <&peri_clk 10>;
 262                         clock-frequency = <400000>;
 263                 };
 264
 265                 system_bus: system-bus@58c00000 {
 266                         compatible = "socionext,uniphier-system-bus";
 267                         status = "disabled";
 268                         reg = <0x58c00000 0x400>;
 269                         #address-cells = <2>;
 270                         #size-cells = <1>;
 271                         pinctrl-names = "default";
 272                         pinctrl-0 = <&pinctrl_system_bus>;
 273                 };
 274
 275                 smpctrl@59801000 {
 276                         compatible = "socionext,uniphier-smpctrl";
 277                         reg = <0x59801000 0x400>;
 278                 };
 279
 280                 sdctrl@59810000 {
 281                         compatible = "socionext,uniphier-pxs3-sdctrl",
 282                                      "simple-mfd", "syscon";
 283                         reg = <0x59810000 0x400>;
 284
 285                         sd_clk: clock {
 286                                 compatible = "socionext,uniphier-pxs3-sd-clock";
 287                                 #clock-cells = <1>;
 288                         };
 289
 290                         sd_rst: reset {
 291                                 compatible = "socionext,uniphier-pxs3-sd-reset";
 292                                 #reset-cells = <1>;
 293                         };
 294                 };
 295
 296                 perictrl@59820000 {
 297                         compatible = "socionext,uniphier-pxs3-perictrl",
 298                                      "simple-mfd", "syscon";
 299                         reg = <0x59820000 0x200>;
 300
 301                         peri_clk: clock {
 302                                 compatible = "socionext,uniphier-pxs3-peri-clock";
 303                                 #clock-cells = <1>;
 304                         };
 305
 306                         peri_rst: reset {
 307                                 compatible = "socionext,uniphier-pxs3-peri-reset";
 308                                 #reset-cells = <1>;
 309                         };
 310                 };
 311
 312                 emmc: sdhc@5a000000 {
 313                         compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
 314                         reg = <0x5a000000 0x400>;
 315                         interrupts = <0 78 4>;
 316                         pinctrl-names = "default";
 317                         pinctrl-0 = <&pinctrl_emmc_1v8>;
 318                         clocks = <&sys_clk 4>;
 319                         bus-width = <8>;
 320                         mmc-ddr-1_8v;
 321                         mmc-hs200-1_8v;
 322                         cdns,phy-input-delay-legacy = <4>;
 323                         cdns,phy-input-delay-mmc-highspeed = <2>;
 324                         cdns,phy-input-delay-mmc-ddr = <3>;
 325                         cdns,phy-dll-delay-sdclk = <21>;
 326                         cdns,phy-dll-delay-sdclk-hsmmc = <21>;
 327                 };
 328
 329                 sd: sdhc@5a400000 {
 330                         compatible = "socionext,uniphier-sdhc";
 331                         status = "disabled";
 332                         reg = <0x5a400000 0x800>;
 333                         interrupts = <0 76 4>;
 334                         pinctrl-names = "default";
 335                         pinctrl-0 = <&pinctrl_sd>;
 336                         clocks = <&sd_clk 0>;
 337                         reset-names = "host";
 338                         resets = <&sd_rst 0>;
 339                         bus-width = <4>;
 340                         cap-sd-highspeed;
 341                 };
 342
 343                 soc-glue@5f800000 {
 344                         compatible = "socionext,uniphier-pxs3-soc-glue",
 345                                      "simple-mfd", "syscon";
 346                         reg = <0x5f800000 0x2000>;
 347
 348                         pinctrl: pinctrl {
 349                                 compatible = "socionext,uniphier-pxs3-pinctrl";
 350                         };
 351                 };
 352
 353                 aidet: aidet@5fc20000 {
 354                         compatible = "socionext,uniphier-pxs3-aidet";
 355                         reg = <0x5fc20000 0x200>;
 356                         interrupt-controller;
 357                         #interrupt-cells = <2>;
 358                 };
 359
 360                 gic: interrupt-controller@5fe00000 {
 361                         compatible = "arm,gic-v3";
 362                         reg = <0x5fe00000 0x10000>,     /* GICD */
 363                               <0x5fe80000 0x80000>;     /* GICR */
 364                         interrupt-controller;
 365                         #interrupt-cells = <3>;
 366                         interrupts = <1 9 4>;
 367                 };
 368
 369                 sysctrl@61840000 {
 370                         compatible = "socionext,uniphier-pxs3-sysctrl",
 371                                      "simple-mfd", "syscon";
 372                         reg = <0x61840000 0x10000>;
 373
 374                         sys_clk: clock {
 375                                 compatible = "socionext,uniphier-pxs3-clock";
 376                                 #clock-cells = <1>;
 377                         };
 378
 379                         sys_rst: reset {
 380                                 compatible = "socionext,uniphier-pxs3-reset";
 381                                 #reset-cells = <1>;
 382                         };
 383
 384                         watchdog {
 385                                 compatible = "socionext,uniphier-wdt";
 386                         };
 387                 };
 388
 389                 usb0: usb@65b00000 {
 390                         compatible = "socionext,uniphier-pxs3-dwc3";
 391                         status = "disabled";
 392                         reg = <0x65b00000 0x1000>;
 393                         #address-cells = <1>;
 394                         #size-cells = <1>;
 395                         ranges;
 396                         pinctrl-names = "default";
 397                         pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
 398                         dwc3@65a00000 {
 399                                 compatible = "snps,dwc3";
 400                                 reg = <0x65a00000 0x10000>;
 401                                 interrupts = <0 134 4>;
 402                                 dr_mode = "host";
 403                                 tx-fifo-resize;
 404                         };
 405                 };
 406
 407                 usb1: usb@65d00000 {
 408                         compatible = "socionext,uniphier-pxs3-dwc3";
 409                         status = "disabled";
 410                         reg = <0x65d00000 0x1000>;
 411                         #address-cells = <1>;
 412                         #size-cells = <1>;
 413                         ranges;
 414                         pinctrl-names = "default";
 415                         pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
 416                         dwc3@65c00000 {
 417                                 compatible = "snps,dwc3";
 418                                 reg = <0x65c00000 0x10000>;
 419                                 interrupts = <0 137 4>;
 420                                 dr_mode = "host";
 421                                 tx-fifo-resize;
 422                         };
 423                 };
 424
 425                 nand: nand@68000000 {
 426                         compatible = "socionext,uniphier-denali-nand-v5b";
 427                         status = "disabled";
 428                         reg-names = "nand_data", "denali_reg";
 429                         reg = <0x68000000 0x20>, <0x68100000 0x1000>;
 430                         interrupts = <0 65 4>;
 431                         pinctrl-names = "default";
 432                         pinctrl-0 = <&pinctrl_nand>;
 433                         clocks = <&sys_clk 2>;
 434                 };
 435         };
 436 };
 437
 438 #include "uniphier-pinctrl.dtsi"