2 * Device Tree Source for UniPhier PXs3 SoC
4 * Copyright (C) 2017 Socionext Inc.
5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
7 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
10 /memreserve/ 0x80000000 0x02000000;
13 compatible = "socionext,uniphier-pxs3";
16 interrupt-parent = <&gic>;
41 compatible = "arm,cortex-a53", "arm,armv8";
43 clocks = <&sys_clk 33>;
44 enable-method = "psci";
45 operating-points-v2 = <&cluster0_opp>;
50 compatible = "arm,cortex-a53", "arm,armv8";
52 clocks = <&sys_clk 33>;
53 enable-method = "psci";
54 operating-points-v2 = <&cluster0_opp>;
59 compatible = "arm,cortex-a53", "arm,armv8";
61 clocks = <&sys_clk 33>;
62 enable-method = "psci";
63 operating-points-v2 = <&cluster0_opp>;
68 compatible = "arm,cortex-a53", "arm,armv8";
70 clocks = <&sys_clk 33>;
71 enable-method = "psci";
72 operating-points-v2 = <&cluster0_opp>;
76 cluster0_opp: opp_table {
77 compatible = "operating-points-v2";
81 opp-hz = /bits/ 64 <250000000>;
82 clock-latency-ns = <300>;
85 opp-hz = /bits/ 64 <325000000>;
86 clock-latency-ns = <300>;
89 opp-hz = /bits/ 64 <500000000>;
90 clock-latency-ns = <300>;
93 opp-hz = /bits/ 64 <650000000>;
94 clock-latency-ns = <300>;
97 opp-hz = /bits/ 64 <666667000>;
98 clock-latency-ns = <300>;
101 opp-hz = /bits/ 64 <866667000>;
102 clock-latency-ns = <300>;
105 opp-hz = /bits/ 64 <1000000000>;
106 clock-latency-ns = <300>;
109 opp-hz = /bits/ 64 <1300000000>;
110 clock-latency-ns = <300>;
115 compatible = "arm,psci-1.0";
121 compatible = "fixed-clock";
123 clock-frequency = <25000000>;
128 compatible = "arm,armv8-timer";
129 interrupts = <1 13 4>,
136 compatible = "simple-bus";
137 #address-cells = <1>;
139 ranges = <0 0 0 0xffffffff>;
141 serial0: serial@54006800 {
142 compatible = "socionext,uniphier-uart";
144 reg = <0x54006800 0x40>;
145 interrupts = <0 33 4>;
146 pinctrl-names = "default";
147 pinctrl-0 = <&pinctrl_uart0>;
148 clocks = <&peri_clk 0>;
149 clock-frequency = <58820000>;
152 serial1: serial@54006900 {
153 compatible = "socionext,uniphier-uart";
155 reg = <0x54006900 0x40>;
156 interrupts = <0 35 4>;
157 pinctrl-names = "default";
158 pinctrl-0 = <&pinctrl_uart1>;
159 clocks = <&peri_clk 1>;
160 clock-frequency = <58820000>;
163 serial2: serial@54006a00 {
164 compatible = "socionext,uniphier-uart";
166 reg = <0x54006a00 0x40>;
167 interrupts = <0 37 4>;
168 pinctrl-names = "default";
169 pinctrl-0 = <&pinctrl_uart2>;
170 clocks = <&peri_clk 2>;
171 clock-frequency = <58820000>;
174 serial3: serial@54006b00 {
175 compatible = "socionext,uniphier-uart";
177 reg = <0x54006b00 0x40>;
178 interrupts = <0 177 4>;
179 pinctrl-names = "default";
180 pinctrl-0 = <&pinctrl_uart3>;
181 clocks = <&peri_clk 3>;
182 clock-frequency = <58820000>;
185 gpio: gpio@55000000 {
186 compatible = "socionext,uniphier-pxs3-gpio";
187 reg = <0x55000000 0x200>;
188 interrupt-parent = <&aidet>;
189 interrupt-controller;
190 #interrupt-cells = <2>;
193 gpio-ranges = <&pinctrl 0 0 0>,
196 gpio-ranges-group-names = "gpio_range0",
202 compatible = "socionext,uniphier-fi2c";
204 reg = <0x58780000 0x80>;
205 #address-cells = <1>;
207 interrupts = <0 41 4>;
208 pinctrl-names = "default";
209 pinctrl-0 = <&pinctrl_i2c0>;
210 clocks = <&peri_clk 4>;
211 clock-frequency = <100000>;
215 compatible = "socionext,uniphier-fi2c";
217 reg = <0x58781000 0x80>;
218 #address-cells = <1>;
220 interrupts = <0 42 4>;
221 pinctrl-names = "default";
222 pinctrl-0 = <&pinctrl_i2c1>;
223 clocks = <&peri_clk 5>;
224 clock-frequency = <100000>;
228 compatible = "socionext,uniphier-fi2c";
230 reg = <0x58782000 0x80>;
231 #address-cells = <1>;
233 interrupts = <0 43 4>;
234 pinctrl-names = "default";
235 pinctrl-0 = <&pinctrl_i2c2>;
236 clocks = <&peri_clk 6>;
237 clock-frequency = <100000>;
241 compatible = "socionext,uniphier-fi2c";
243 reg = <0x58783000 0x80>;
244 #address-cells = <1>;
246 interrupts = <0 44 4>;
247 pinctrl-names = "default";
248 pinctrl-0 = <&pinctrl_i2c3>;
249 clocks = <&peri_clk 7>;
250 clock-frequency = <100000>;
253 /* chip-internal connection for HDMI */
255 compatible = "socionext,uniphier-fi2c";
256 reg = <0x58786000 0x80>;
257 #address-cells = <1>;
259 interrupts = <0 26 4>;
260 clocks = <&peri_clk 10>;
261 clock-frequency = <400000>;
264 system_bus: system-bus@58c00000 {
265 compatible = "socionext,uniphier-system-bus";
267 reg = <0x58c00000 0x400>;
268 #address-cells = <2>;
270 pinctrl-names = "default";
271 pinctrl-0 = <&pinctrl_system_bus>;
275 compatible = "socionext,uniphier-smpctrl";
276 reg = <0x59801000 0x400>;
280 compatible = "socionext,uniphier-pxs3-sdctrl",
281 "simple-mfd", "syscon";
282 reg = <0x59810000 0x400>;
285 compatible = "socionext,uniphier-pxs3-sd-clock";
290 compatible = "socionext,uniphier-pxs3-sd-reset";
296 compatible = "socionext,uniphier-pxs3-perictrl",
297 "simple-mfd", "syscon";
298 reg = <0x59820000 0x200>;
301 compatible = "socionext,uniphier-pxs3-peri-clock";
306 compatible = "socionext,uniphier-pxs3-peri-reset";
311 emmc: sdhc@5a000000 {
312 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
313 reg = <0x5a000000 0x400>;
314 interrupts = <0 78 4>;
315 pinctrl-names = "default";
316 pinctrl-0 = <&pinctrl_emmc_1v8>;
317 clocks = <&sys_clk 4>;
321 cdns,phy-input-delay-legacy = <4>;
322 cdns,phy-input-delay-mmc-highspeed = <2>;
323 cdns,phy-input-delay-mmc-ddr = <3>;
324 cdns,phy-dll-delay-sdclk = <21>;
325 cdns,phy-dll-delay-sdclk-hsmmc = <21>;
329 compatible = "socionext,uniphier-sdhc";
331 reg = <0x5a400000 0x800>;
332 interrupts = <0 76 4>;
333 pinctrl-names = "default";
334 pinctrl-0 = <&pinctrl_sd>;
335 clocks = <&sd_clk 0>;
336 reset-names = "host";
337 resets = <&sd_rst 0>;
343 compatible = "socionext,uniphier-pxs3-soc-glue",
344 "simple-mfd", "syscon";
345 reg = <0x5f800000 0x2000>;
348 compatible = "socionext,uniphier-pxs3-pinctrl";
352 aidet: aidet@5fc20000 {
353 compatible = "socionext,uniphier-pxs3-aidet";
354 reg = <0x5fc20000 0x200>;
355 interrupt-controller;
356 #interrupt-cells = <2>;
359 gic: interrupt-controller@5fe00000 {
360 compatible = "arm,gic-v3";
361 reg = <0x5fe00000 0x10000>, /* GICD */
362 <0x5fe80000 0x80000>; /* GICR */
363 interrupt-controller;
364 #interrupt-cells = <3>;
365 interrupts = <1 9 4>;
369 compatible = "socionext,uniphier-pxs3-sysctrl",
370 "simple-mfd", "syscon";
371 reg = <0x61840000 0x10000>;
374 compatible = "socionext,uniphier-pxs3-clock";
379 compatible = "socionext,uniphier-pxs3-reset";
384 compatible = "socionext,uniphier-wdt";
389 compatible = "socionext,uniphier-pxs3-dwc3";
391 reg = <0x65b00000 0x1000>;
392 #address-cells = <1>;
395 pinctrl-names = "default";
396 pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
398 compatible = "snps,dwc3";
399 reg = <0x65a00000 0x10000>;
400 interrupts = <0 134 4>;
407 compatible = "socionext,uniphier-pxs3-dwc3";
409 reg = <0x65d00000 0x1000>;
410 #address-cells = <1>;
413 pinctrl-names = "default";
414 pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
416 compatible = "snps,dwc3";
417 reg = <0x65c00000 0x10000>;
418 interrupts = <0 137 4>;
424 nand: nand@68000000 {
425 compatible = "socionext,uniphier-denali-nand-v5b";
427 reg-names = "nand_data", "denali_reg";
428 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
429 interrupts = <0 65 4>;
430 pinctrl-names = "default";
431 pinctrl-0 = <&pinctrl_nand>;
432 clocks = <&sys_clk 2>;
437 #include "uniphier-pinctrl.dtsi"