2 * Device Tree Source for UniPhier PXs3 SoC
4 * Copyright (C) 2017 Socionext Inc.
5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
7 * This file is dual-licensed: you can use it either under the terms
8 * of the GPL or the X11 license, at your option. Note that this dual
9 * licensing only applies to this file, and not this project as a
12 * a) This file is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of the
15 * License, or (at your option) any later version.
17 * This file is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
24 * b) Permission is hereby granted, free of charge, to any person
25 * obtaining a copy of this software and associated documentation
26 * files (the "Software"), to deal in the Software without
27 * restriction, including without limitation the rights to use,
28 * copy, modify, merge, publish, distribute, sublicense, and/or
29 * sell copies of the Software, and to permit persons to whom the
30 * Software is furnished to do so, subject to the following
33 * The above copyright notice and this permission notice shall be
34 * included in all copies or substantial portions of the Software.
36 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
37 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
38 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
39 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
40 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
41 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
42 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
43 * OTHER DEALINGS IN THE SOFTWARE.
46 /memreserve/ 0x80000000 0x00080000;
49 compatible = "socionext,uniphier-pxs3";
52 interrupt-parent = <&gic>;
77 compatible = "arm,cortex-a53", "arm,armv8";
79 enable-method = "psci";
84 compatible = "arm,cortex-a53", "arm,armv8";
86 enable-method = "psci";
91 compatible = "arm,cortex-a53", "arm,armv8";
93 enable-method = "psci";
98 compatible = "arm,cortex-a53", "arm,armv8";
100 enable-method = "psci";
105 compatible = "arm,psci-1.0";
111 compatible = "fixed-clock";
113 clock-frequency = <25000000>;
118 compatible = "arm,armv8-timer";
119 interrupts = <1 13 4>,
126 compatible = "simple-bus";
127 #address-cells = <1>;
129 ranges = <0 0 0 0xffffffff>;
131 serial0: serial@54006800 {
132 compatible = "socionext,uniphier-uart";
134 reg = <0x54006800 0x40>;
135 interrupts = <0 33 4>;
136 pinctrl-names = "default";
137 pinctrl-0 = <&pinctrl_uart0>;
138 clocks = <&peri_clk 0>;
139 clock-frequency = <58820000>;
142 serial1: serial@54006900 {
143 compatible = "socionext,uniphier-uart";
145 reg = <0x54006900 0x40>;
146 interrupts = <0 35 4>;
147 pinctrl-names = "default";
148 pinctrl-0 = <&pinctrl_uart1>;
149 clocks = <&peri_clk 1>;
150 clock-frequency = <58820000>;
153 serial2: serial@54006a00 {
154 compatible = "socionext,uniphier-uart";
156 reg = <0x54006a00 0x40>;
157 interrupts = <0 37 4>;
158 pinctrl-names = "default";
159 pinctrl-0 = <&pinctrl_uart2>;
160 clocks = <&peri_clk 2>;
161 clock-frequency = <58820000>;
164 serial3: serial@54006b00 {
165 compatible = "socionext,uniphier-uart";
167 reg = <0x54006b00 0x40>;
168 interrupts = <0 177 4>;
169 pinctrl-names = "default";
170 pinctrl-0 = <&pinctrl_uart3>;
171 clocks = <&peri_clk 3>;
172 clock-frequency = <58820000>;
176 compatible = "socionext,uniphier-fi2c";
178 reg = <0x58780000 0x80>;
179 #address-cells = <1>;
181 interrupts = <0 41 4>;
182 pinctrl-names = "default";
183 pinctrl-0 = <&pinctrl_i2c0>;
184 clocks = <&peri_clk 4>;
185 clock-frequency = <100000>;
189 compatible = "socionext,uniphier-fi2c";
191 reg = <0x58781000 0x80>;
192 #address-cells = <1>;
194 interrupts = <0 42 4>;
195 pinctrl-names = "default";
196 pinctrl-0 = <&pinctrl_i2c1>;
197 clocks = <&peri_clk 5>;
198 clock-frequency = <100000>;
202 compatible = "socionext,uniphier-fi2c";
204 reg = <0x58782000 0x80>;
205 #address-cells = <1>;
207 interrupts = <0 43 4>;
208 clocks = <&peri_clk 6>;
209 clock-frequency = <100000>;
213 compatible = "socionext,uniphier-fi2c";
215 reg = <0x58783000 0x80>;
216 #address-cells = <1>;
218 interrupts = <0 44 4>;
219 pinctrl-names = "default";
220 pinctrl-0 = <&pinctrl_i2c3>;
221 clocks = <&peri_clk 7>;
222 clock-frequency = <100000>;
225 /* chip-internal connection for HDMI */
227 compatible = "socionext,uniphier-fi2c";
228 reg = <0x58786000 0x80>;
229 #address-cells = <1>;
231 interrupts = <0 26 4>;
232 clocks = <&peri_clk 10>;
233 clock-frequency = <400000>;
236 system_bus: system-bus@58c00000 {
237 compatible = "socionext,uniphier-system-bus";
239 reg = <0x58c00000 0x400>;
240 #address-cells = <2>;
242 pinctrl-names = "default";
243 pinctrl-0 = <&pinctrl_system_bus>;
247 compatible = "socionext,uniphier-smpctrl";
248 reg = <0x59801000 0x400>;
252 compatible = "socionext,uniphier-pxs3-sdctrl",
253 "simple-mfd", "syscon";
254 reg = <0x59810000 0x800>;
257 compatible = "socionext,uniphier-pxs3-sd-clock";
262 compatible = "socionext,uniphier-pxs3-sd-reset";
268 compatible = "socionext,uniphier-pxs3-perictrl",
269 "simple-mfd", "syscon";
270 reg = <0x59820000 0x200>;
273 compatible = "socionext,uniphier-pxs3-peri-clock";
278 compatible = "socionext,uniphier-pxs3-peri-reset";
283 emmc: sdhc@5a000000 {
284 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
286 reg = <0x5a000000 0x400>;
287 interrupts = <0 78 4>;
288 pinctrl-names = "default";
289 pinctrl-0 = <&pinctrl_emmc_1v8>;
290 clocks = <&sys_clk 4>;
297 compatible = "socionext,uniphier-sdhc";
299 reg = <0x5a400000 0x800>;
300 interrupts = <0 76 4>;
301 pinctrl-names = "default";
302 pinctrl-0 = <&pinctrl_sd>;
303 clocks = <&sd_clk 0>;
304 reset-names = "host";
305 resets = <&sd_rst 0>;
311 compatible = "socionext,uniphier-pxs3-soc-glue",
312 "simple-mfd", "syscon";
313 reg = <0x5f800000 0x2000>;
316 compatible = "socionext,uniphier-pxs3-pinctrl";
321 compatible = "simple-mfd", "syscon";
322 reg = <0x5fc20000 0x200>;
325 gic: interrupt-controller@5fe00000 {
326 compatible = "arm,gic-v3";
327 reg = <0x5fe00000 0x10000>, /* GICD */
328 <0x5fe80000 0x80000>; /* GICR */
329 interrupt-controller;
330 #interrupt-cells = <3>;
331 interrupts = <1 9 4>;
335 compatible = "socionext,uniphier-pxs3-sysctrl",
336 "simple-mfd", "syscon";
337 reg = <0x61840000 0x10000>;
340 compatible = "socionext,uniphier-pxs3-clock";
345 compatible = "socionext,uniphier-pxs3-reset";
350 nand: nand@68000000 {
351 compatible = "socionext,denali-nand-v5b";
353 reg-names = "nand_data", "denali_reg";
354 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
355 interrupts = <0 65 4>;
356 pinctrl-names = "default";
357 pinctrl-0 = <&pinctrl_nand>;
358 clocks = <&sys_clk 2>;
359 nand-ecc-strength = <8>;
364 /include/ "uniphier-pinctrl.dtsi"