2 * Device Tree Source for UniPhier PXs3 SoC
4 * Copyright (C) 2017 Socionext Inc.
5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
7 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/gpio/uniphier-gpio.h>
13 /memreserve/ 0x80000000 0x02000000;
16 compatible = "socionext,uniphier-pxs3";
19 interrupt-parent = <&gic>;
44 compatible = "arm,cortex-a53", "arm,armv8";
46 clocks = <&sys_clk 33>;
47 enable-method = "psci";
48 operating-points-v2 = <&cluster0_opp>;
53 compatible = "arm,cortex-a53", "arm,armv8";
55 clocks = <&sys_clk 33>;
56 enable-method = "psci";
57 operating-points-v2 = <&cluster0_opp>;
62 compatible = "arm,cortex-a53", "arm,armv8";
64 clocks = <&sys_clk 33>;
65 enable-method = "psci";
66 operating-points-v2 = <&cluster0_opp>;
71 compatible = "arm,cortex-a53", "arm,armv8";
73 clocks = <&sys_clk 33>;
74 enable-method = "psci";
75 operating-points-v2 = <&cluster0_opp>;
79 cluster0_opp: opp-table {
80 compatible = "operating-points-v2";
84 opp-hz = /bits/ 64 <250000000>;
85 clock-latency-ns = <300>;
88 opp-hz = /bits/ 64 <325000000>;
89 clock-latency-ns = <300>;
92 opp-hz = /bits/ 64 <500000000>;
93 clock-latency-ns = <300>;
96 opp-hz = /bits/ 64 <650000000>;
97 clock-latency-ns = <300>;
100 opp-hz = /bits/ 64 <666667000>;
101 clock-latency-ns = <300>;
104 opp-hz = /bits/ 64 <866667000>;
105 clock-latency-ns = <300>;
108 opp-hz = /bits/ 64 <1000000000>;
109 clock-latency-ns = <300>;
112 opp-hz = /bits/ 64 <1300000000>;
113 clock-latency-ns = <300>;
118 compatible = "arm,psci-1.0";
124 compatible = "fixed-clock";
126 clock-frequency = <25000000>;
130 emmc_pwrseq: emmc-pwrseq {
131 compatible = "mmc-pwrseq-emmc";
132 reset-gpios = <&gpio UNIPHIER_GPIO_PORT(5, 7) GPIO_ACTIVE_LOW>;
136 compatible = "arm,armv8-timer";
137 interrupts = <1 13 4>,
144 compatible = "simple-bus";
145 #address-cells = <1>;
147 ranges = <0 0 0 0xffffffff>;
149 serial0: serial@54006800 {
150 compatible = "socionext,uniphier-uart";
152 reg = <0x54006800 0x40>;
153 interrupts = <0 33 4>;
154 pinctrl-names = "default";
155 pinctrl-0 = <&pinctrl_uart0>;
156 clocks = <&peri_clk 0>;
157 clock-frequency = <58820000>;
158 resets = <&peri_rst 0>;
161 serial1: serial@54006900 {
162 compatible = "socionext,uniphier-uart";
164 reg = <0x54006900 0x40>;
165 interrupts = <0 35 4>;
166 pinctrl-names = "default";
167 pinctrl-0 = <&pinctrl_uart1>;
168 clocks = <&peri_clk 1>;
169 clock-frequency = <58820000>;
170 resets = <&peri_rst 1>;
173 serial2: serial@54006a00 {
174 compatible = "socionext,uniphier-uart";
176 reg = <0x54006a00 0x40>;
177 interrupts = <0 37 4>;
178 pinctrl-names = "default";
179 pinctrl-0 = <&pinctrl_uart2>;
180 clocks = <&peri_clk 2>;
181 clock-frequency = <58820000>;
182 resets = <&peri_rst 2>;
185 serial3: serial@54006b00 {
186 compatible = "socionext,uniphier-uart";
188 reg = <0x54006b00 0x40>;
189 interrupts = <0 177 4>;
190 pinctrl-names = "default";
191 pinctrl-0 = <&pinctrl_uart3>;
192 clocks = <&peri_clk 3>;
193 clock-frequency = <58820000>;
194 resets = <&peri_rst 3>;
197 gpio: gpio@55000000 {
198 compatible = "socionext,uniphier-gpio";
199 reg = <0x55000000 0x200>;
200 interrupt-parent = <&aidet>;
201 interrupt-controller;
202 #interrupt-cells = <2>;
205 gpio-ranges = <&pinctrl 0 0 0>,
208 gpio-ranges-group-names = "gpio_range0",
212 socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
217 compatible = "socionext,uniphier-fi2c";
219 reg = <0x58780000 0x80>;
220 #address-cells = <1>;
222 interrupts = <0 41 4>;
223 pinctrl-names = "default";
224 pinctrl-0 = <&pinctrl_i2c0>;
225 clocks = <&peri_clk 4>;
226 resets = <&peri_rst 4>;
227 clock-frequency = <100000>;
231 compatible = "socionext,uniphier-fi2c";
233 reg = <0x58781000 0x80>;
234 #address-cells = <1>;
236 interrupts = <0 42 4>;
237 pinctrl-names = "default";
238 pinctrl-0 = <&pinctrl_i2c1>;
239 clocks = <&peri_clk 5>;
240 resets = <&peri_rst 5>;
241 clock-frequency = <100000>;
245 compatible = "socionext,uniphier-fi2c";
247 reg = <0x58782000 0x80>;
248 #address-cells = <1>;
250 interrupts = <0 43 4>;
251 pinctrl-names = "default";
252 pinctrl-0 = <&pinctrl_i2c2>;
253 clocks = <&peri_clk 6>;
254 resets = <&peri_rst 6>;
255 clock-frequency = <100000>;
259 compatible = "socionext,uniphier-fi2c";
261 reg = <0x58783000 0x80>;
262 #address-cells = <1>;
264 interrupts = <0 44 4>;
265 pinctrl-names = "default";
266 pinctrl-0 = <&pinctrl_i2c3>;
267 clocks = <&peri_clk 7>;
268 resets = <&peri_rst 7>;
269 clock-frequency = <100000>;
272 /* chip-internal connection for HDMI */
274 compatible = "socionext,uniphier-fi2c";
275 reg = <0x58786000 0x80>;
276 #address-cells = <1>;
278 interrupts = <0 26 4>;
279 clocks = <&peri_clk 10>;
280 resets = <&peri_rst 10>;
281 clock-frequency = <400000>;
284 system_bus: system-bus@58c00000 {
285 compatible = "socionext,uniphier-system-bus";
287 reg = <0x58c00000 0x400>;
288 #address-cells = <2>;
290 pinctrl-names = "default";
291 pinctrl-0 = <&pinctrl_system_bus>;
295 compatible = "socionext,uniphier-smpctrl";
296 reg = <0x59801000 0x400>;
300 compatible = "socionext,uniphier-pxs3-sdctrl",
301 "simple-mfd", "syscon";
302 reg = <0x59810000 0x400>;
305 compatible = "socionext,uniphier-pxs3-sd-clock";
310 compatible = "socionext,uniphier-pxs3-sd-reset";
316 compatible = "socionext,uniphier-pxs3-perictrl",
317 "simple-mfd", "syscon";
318 reg = <0x59820000 0x200>;
321 compatible = "socionext,uniphier-pxs3-peri-clock";
326 compatible = "socionext,uniphier-pxs3-peri-reset";
331 emmc: sdhc@5a000000 {
332 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
333 reg = <0x5a000000 0x400>;
334 interrupts = <0 78 4>;
335 pinctrl-names = "default";
336 pinctrl-0 = <&pinctrl_emmc_1v8>;
337 clocks = <&sys_clk 4>;
338 resets = <&sys_rst 4>;
342 mmc-pwrseq = <&emmc_pwrseq>;
343 cdns,phy-input-delay-legacy = <4>;
344 cdns,phy-input-delay-mmc-highspeed = <2>;
345 cdns,phy-input-delay-mmc-ddr = <3>;
346 cdns,phy-dll-delay-sdclk = <21>;
347 cdns,phy-dll-delay-sdclk-hsmmc = <21>;
351 compatible = "socionext,uniphier-sdhc";
353 reg = <0x5a400000 0x800>;
354 interrupts = <0 76 4>;
355 pinctrl-names = "default";
356 pinctrl-0 = <&pinctrl_sd>;
357 clocks = <&sd_clk 0>;
358 reset-names = "host";
359 resets = <&sd_rst 0>;
365 compatible = "socionext,uniphier-pxs3-soc-glue",
366 "simple-mfd", "syscon";
367 reg = <0x5f800000 0x2000>;
370 compatible = "socionext,uniphier-pxs3-pinctrl";
375 compatible = "socionext,uniphier-pxs3-soc-glue-debug",
377 #address-cells = <1>;
379 ranges = <0 0x5f900000 0x2000>;
382 compatible = "socionext,uniphier-efuse";
387 compatible = "socionext,uniphier-efuse";
392 aidet: aidet@5fc20000 {
393 compatible = "socionext,uniphier-pxs3-aidet";
394 reg = <0x5fc20000 0x200>;
395 interrupt-controller;
396 #interrupt-cells = <2>;
399 gic: interrupt-controller@5fe00000 {
400 compatible = "arm,gic-v3";
401 reg = <0x5fe00000 0x10000>, /* GICD */
402 <0x5fe80000 0x80000>; /* GICR */
403 interrupt-controller;
404 #interrupt-cells = <3>;
405 interrupts = <1 9 4>;
409 compatible = "socionext,uniphier-pxs3-sysctrl",
410 "simple-mfd", "syscon";
411 reg = <0x61840000 0x10000>;
414 compatible = "socionext,uniphier-pxs3-clock";
419 compatible = "socionext,uniphier-pxs3-reset";
424 compatible = "socionext,uniphier-wdt";
429 compatible = "socionext,uniphier-pxs3-dwc3";
431 reg = <0x65b00000 0x1000>;
432 #address-cells = <1>;
435 pinctrl-names = "default";
436 pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
438 compatible = "snps,dwc3";
439 reg = <0x65a00000 0x10000>;
440 interrupts = <0 134 4>;
447 compatible = "socionext,uniphier-pxs3-dwc3";
449 reg = <0x65d00000 0x1000>;
450 #address-cells = <1>;
453 pinctrl-names = "default";
454 pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
456 compatible = "snps,dwc3";
457 reg = <0x65c00000 0x10000>;
458 interrupts = <0 137 4>;
464 nand: nand@68000000 {
465 compatible = "socionext,uniphier-denali-nand-v5b";
467 reg-names = "nand_data", "denali_reg";
468 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
469 interrupts = <0 65 4>;
470 pinctrl-names = "default";
471 pinctrl-0 = <&pinctrl_nand>;
472 clocks = <&sys_clk 2>;
473 resets = <&sys_rst 2>;
478 #include "uniphier-pinctrl.dtsi"