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1 /*
2  * Device Tree Source for UniPhier sLD3 SoC
3  *
4  * Copyright (C) 2015-2016 Socionext Inc.
5  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
6  *
7  * SPDX-License-Identifier:     GPL-2.0+        X11
8  */
9
10 / {
11         compatible = "socionext,uniphier-sld3";
12         #address-cells = <1>;
13         #size-cells = <1>;
14
15         cpus {
16                 #address-cells = <1>;
17                 #size-cells = <0>;
18
19                 cpu@0 {
20                         device_type = "cpu";
21                         compatible = "arm,cortex-a9";
22                         reg = <0>;
23                         enable-method = "psci";
24                         next-level-cache = <&l2>;
25                 };
26
27                 cpu@1 {
28                         device_type = "cpu";
29                         compatible = "arm,cortex-a9";
30                         reg = <1>;
31                         enable-method = "psci";
32                         next-level-cache = <&l2>;
33                 };
34         };
35
36         psci {
37                 compatible = "arm,psci-0.2";
38                 method = "smc";
39         };
40
41         clocks {
42                 refclk: ref {
43                         #clock-cells = <0>;
44                         compatible = "fixed-clock";
45                         clock-frequency = <24576000>;
46                 };
47
48                 arm_timer_clk: arm_timer_clk {
49                         #clock-cells = <0>;
50                         compatible = "fixed-clock";
51                         clock-frequency = <50000000>;
52                 };
53         };
54
55         soc {
56                 compatible = "simple-bus";
57                 #address-cells = <1>;
58                 #size-cells = <1>;
59                 ranges;
60                 interrupt-parent = <&intc>;
61                 u-boot,dm-pre-reloc;
62
63                 timer@20000200 {
64                         compatible = "arm,cortex-a9-global-timer";
65                         reg = <0x20000200 0x20>;
66                         interrupts = <1 11 0x304>;
67                         clocks = <&arm_timer_clk>;
68                 };
69
70                 timer@20000600 {
71                         compatible = "arm,cortex-a9-twd-timer";
72                         reg = <0x20000600 0x20>;
73                         interrupts = <1 13 0x304>;
74                         clocks = <&arm_timer_clk>;
75                 };
76
77                 intc: interrupt-controller@20001000 {
78                         compatible = "arm,cortex-a9-gic";
79                         #interrupt-cells = <3>;
80                         interrupt-controller;
81                         reg = <0x20001000 0x1000>,
82                               <0x20000100 0x100>;
83                 };
84
85                 l2: l2-cache@500c0000 {
86                         compatible = "socionext,uniphier-system-cache";
87                         reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
88                               <0x506c0000 0x400>;
89                         interrupts = <0 174 4>, <0 175 4>;
90                         cache-unified;
91                         cache-size = <(512 * 1024)>;
92                         cache-sets = <256>;
93                         cache-line-size = <128>;
94                         cache-level = <2>;
95                 };
96
97                 serial0: serial@54006800 {
98                         compatible = "socionext,uniphier-uart";
99                         status = "disabled";
100                         reg = <0x54006800 0x40>;
101                         interrupts = <0 33 4>;
102                         pinctrl-names = "default";
103                         pinctrl-0 = <&pinctrl_uart0>;
104                         clocks = <&sys_clk 0>;
105                         clock-frequency = <36864000>;
106                 };
107
108                 serial1: serial@54006900 {
109                         compatible = "socionext,uniphier-uart";
110                         status = "disabled";
111                         reg = <0x54006900 0x40>;
112                         interrupts = <0 35 4>;
113                         pinctrl-names = "default";
114                         pinctrl-0 = <&pinctrl_uart1>;
115                         clocks = <&sys_clk 0>;
116                         clock-frequency = <36864000>;
117                 };
118
119                 serial2: serial@54006a00 {
120                         compatible = "socionext,uniphier-uart";
121                         status = "disabled";
122                         reg = <0x54006a00 0x40>;
123                         interrupts = <0 37 4>;
124                         pinctrl-names = "default";
125                         pinctrl-0 = <&pinctrl_uart2>;
126                         clocks = <&sys_clk 0>;
127                         clock-frequency = <36864000>;
128                 };
129
130                 port0x: gpio@55000008 {
131                         compatible = "socionext,uniphier-gpio";
132                         reg = <0x55000008 0x8>;
133                         gpio-controller;
134                         #gpio-cells = <2>;
135                 };
136
137                 port1x: gpio@55000010 {
138                         compatible = "socionext,uniphier-gpio";
139                         reg = <0x55000010 0x8>;
140                         gpio-controller;
141                         #gpio-cells = <2>;
142                 };
143
144                 port2x: gpio@55000018 {
145                         compatible = "socionext,uniphier-gpio";
146                         reg = <0x55000018 0x8>;
147                         gpio-controller;
148                         #gpio-cells = <2>;
149                 };
150
151                 port3x: gpio@55000020 {
152                         compatible = "socionext,uniphier-gpio";
153                         reg = <0x55000020 0x8>;
154                         gpio-controller;
155                         #gpio-cells = <2>;
156                 };
157
158                 port4: gpio@55000028 {
159                         compatible = "socionext,uniphier-gpio";
160                         reg = <0x55000028 0x8>;
161                         gpio-controller;
162                         #gpio-cells = <2>;
163                 };
164
165                 port5x: gpio@55000030 {
166                         compatible = "socionext,uniphier-gpio";
167                         reg = <0x55000030 0x8>;
168                         gpio-controller;
169                         #gpio-cells = <2>;
170                 };
171
172                 port6x: gpio@55000038 {
173                         compatible = "socionext,uniphier-gpio";
174                         reg = <0x55000038 0x8>;
175                         gpio-controller;
176                         #gpio-cells = <2>;
177                 };
178
179                 port7x: gpio@55000040 {
180                         compatible = "socionext,uniphier-gpio";
181                         reg = <0x55000040 0x8>;
182                         gpio-controller;
183                         #gpio-cells = <2>;
184                 };
185
186                 port8x: gpio@55000048 {
187                         compatible = "socionext,uniphier-gpio";
188                         reg = <0x55000048 0x8>;
189                         gpio-controller;
190                         #gpio-cells = <2>;
191                 };
192
193                 port9x: gpio@55000050 {
194                         compatible = "socionext,uniphier-gpio";
195                         reg = <0x55000050 0x8>;
196                         gpio-controller;
197                         #gpio-cells = <2>;
198                 };
199
200                 port10x: gpio@55000058 {
201                         compatible = "socionext,uniphier-gpio";
202                         reg = <0x55000058 0x8>;
203                         gpio-controller;
204                         #gpio-cells = <2>;
205                 };
206
207                 port11x: gpio@55000060 {
208                         compatible = "socionext,uniphier-gpio";
209                         reg = <0x55000060 0x8>;
210                         gpio-controller;
211                         #gpio-cells = <2>;
212                 };
213
214                 port12x: gpio@55000068 {
215                         compatible = "socionext,uniphier-gpio";
216                         reg = <0x55000068 0x8>;
217                         gpio-controller;
218                         #gpio-cells = <2>;
219                 };
220
221                 port13x: gpio@55000070 {
222                         compatible = "socionext,uniphier-gpio";
223                         reg = <0x55000070 0x8>;
224                         gpio-controller;
225                         #gpio-cells = <2>;
226                 };
227
228                 port14x: gpio@55000078 {
229                         compatible = "socionext,uniphier-gpio";
230                         reg = <0x55000078 0x8>;
231                         gpio-controller;
232                         #gpio-cells = <2>;
233                 };
234
235                 port16x: gpio@55000088 {
236                         compatible = "socionext,uniphier-gpio";
237                         reg = <0x55000088 0x8>;
238                         gpio-controller;
239                         #gpio-cells = <2>;
240                 };
241
242                 i2c0: i2c@58400000 {
243                         compatible = "socionext,uniphier-i2c";
244                         status = "disabled";
245                         reg = <0x58400000 0x40>;
246                         #address-cells = <1>;
247                         #size-cells = <0>;
248                         interrupts = <0 41 1>;
249                         pinctrl-names = "default";
250                         pinctrl-0 = <&pinctrl_i2c0>;
251                         clocks = <&sys_clk 1>;
252                         clock-frequency = <100000>;
253                 };
254
255                 i2c1: i2c@58480000 {
256                         compatible = "socionext,uniphier-i2c";
257                         status = "disabled";
258                         reg = <0x58480000 0x40>;
259                         #address-cells = <1>;
260                         #size-cells = <0>;
261                         interrupts = <0 42 1>;
262                         clocks = <&sys_clk 1>;
263                         clock-frequency = <100000>;
264                 };
265
266                 i2c2: i2c@58500000 {
267                         compatible = "socionext,uniphier-i2c";
268                         status = "disabled";
269                         reg = <0x58500000 0x40>;
270                         #address-cells = <1>;
271                         #size-cells = <0>;
272                         interrupts = <0 43 1>;
273                         clocks = <&sys_clk 1>;
274                         clock-frequency = <100000>;
275                 };
276
277                 i2c3: i2c@58580000 {
278                         compatible = "socionext,uniphier-i2c";
279                         status = "disabled";
280                         reg = <0x58580000 0x40>;
281                         #address-cells = <1>;
282                         #size-cells = <0>;
283                         interrupts = <0 44 1>;
284                         clocks = <&sys_clk 1>;
285                         clock-frequency = <100000>;
286                 };
287
288                 /* chip-internal connection for DMD */
289                 i2c4: i2c@58600000 {
290                         compatible = "socionext,uniphier-i2c";
291                         reg = <0x58600000 0x40>;
292                         #address-cells = <1>;
293                         #size-cells = <0>;
294                         interrupts = <0 45 1>;
295                         clocks = <&sys_clk 1>;
296                         clock-frequency = <400000>;
297                 };
298
299                 system_bus: system-bus@58c00000 {
300                         compatible = "socionext,uniphier-system-bus";
301                         status = "disabled";
302                         reg = <0x58c00000 0x400>;
303                         #address-cells = <2>;
304                         #size-cells = <1>;
305                 };
306
307                 smpctrl@59800000 {
308                         compatible = "socionext,uniphier-smpctrl";
309                         reg = <0x59801000 0x400>;
310                 };
311
312                 mioctrl@59810000 {
313                         compatible = "socionext,uniphier-sld3-mioctrl",
314                                      "simple-mfd", "syscon";
315                         reg = <0x59810000 0x800>;
316                         u-boot,dm-pre-reloc;
317
318                         mio_clk: clock {
319                                 compatible = "socionext,uniphier-sld3-mio-clock";
320                                 #clock-cells = <1>;
321                                 u-boot,dm-pre-reloc;
322                         };
323
324                         mio_rst: reset {
325                                 compatible = "socionext,uniphier-sld3-mio-reset";
326                                 #reset-cells = <1>;
327                         };
328                 };
329
330                 emmc: sdhc@5a400000 {
331                         compatible = "socionext,uniphier-sdhc";
332                         status = "disabled";
333                         reg = <0x5a400000 0x200>;
334                         interrupts = <0 78 4>;
335                         pinctrl-names = "default", "1.8v";
336                         pinctrl-0 = <&pinctrl_emmc>;
337                         pinctrl-1 = <&pinctrl_emmc_1v8>;
338                         clocks = <&mio_clk 1>;
339                         reset-names = "host", "bridge";
340                         resets = <&mio_rst 1>, <&mio_rst 4>;
341                         bus-width = <8>;
342                         non-removable;
343                         cap-mmc-highspeed;
344                         cap-mmc-hw-reset;
345                 };
346
347                 sd: sdhc@5a500000 {
348                         compatible = "socionext,uniphier-sdhc";
349                         status = "disabled";
350                         reg = <0x5a500000 0x200>;
351                         interrupts = <0 76 4>;
352                         pinctrl-names = "default", "1.8v";
353                         pinctrl-0 = <&pinctrl_sd>;
354                         pinctrl-1 = <&pinctrl_sd_1v8>;
355                         clocks = <&mio_clk 0>;
356                         reset-names = "host", "bridge";
357                         resets = <&mio_rst 0>, <&mio_rst 3>;
358                         bus-width = <4>;
359                         cap-sd-highspeed;
360                         sd-uhs-sdr12;
361                         sd-uhs-sdr25;
362                         sd-uhs-sdr50;
363                 };
364
365                 usb0: usb@5a800100 {
366                         compatible = "socionext,uniphier-ehci", "generic-ehci";
367                         status = "disabled";
368                         reg = <0x5a800100 0x100>;
369                         interrupts = <0 80 4>;
370                         pinctrl-names = "default";
371                         pinctrl-0 = <&pinctrl_usb0>;
372                         clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
373                         resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
374                                  <&mio_rst 12>;
375                 };
376
377                 usb1: usb@5a810100 {
378                         compatible = "socionext,uniphier-ehci", "generic-ehci";
379                         status = "disabled";
380                         reg = <0x5a810100 0x100>;
381                         interrupts = <0 81 4>;
382                         pinctrl-names = "default";
383                         pinctrl-0 = <&pinctrl_usb1>;
384                         clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
385                         resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
386                                  <&mio_rst 13>;
387                 };
388
389                 usb2: usb@5a820100 {
390                         compatible = "socionext,uniphier-ehci", "generic-ehci";
391                         status = "disabled";
392                         reg = <0x5a820100 0x100>;
393                         interrupts = <0 82 4>;
394                         pinctrl-names = "default";
395                         pinctrl-0 = <&pinctrl_usb2>;
396                         clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>;
397                         resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
398                                  <&mio_rst 14>;
399                 };
400
401                 usb3: usb@5a830100 {
402                         compatible = "socionext,uniphier-ehci", "generic-ehci";
403                         status = "disabled";
404                         reg = <0x5a830100 0x100>;
405                         interrupts = <0 83 4>;
406                         pinctrl-names = "default";
407                         pinctrl-0 = <&pinctrl_usb3>;
408                         clocks = <&mio_clk 7>, <&mio_clk 11>, <&mio_clk 15>;
409                         resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 11>,
410                                  <&mio_rst 15>;
411                 };
412
413                 soc-glue@5f800000 {
414                         compatible = "socionext,uniphier-sld3-soc-glue",
415                                      "simple-mfd", "syscon";
416                         reg = <0x5f800000 0x2000>;
417                         u-boot,dm-pre-reloc;
418
419                         pinctrl: pinctrl {
420                                 compatible = "socionext,uniphier-sld3-pinctrl";
421                                 u-boot,dm-pre-reloc;
422                         };
423                 };
424
425                 aidet@f1830000 {
426                         compatible = "simple-mfd", "syscon";
427                         reg = <0xf1830000 0x200>;
428                 };
429
430                 sysctrl@f1840000 {
431                         compatible = "socionext,uniphier-sld3-sysctrl",
432                                      "simple-mfd", "syscon";
433                         reg = <0xf1840000 0x10000>;
434
435                         sys_clk: clock {
436                                 compatible = "socionext,uniphier-sld3-clock";
437                                 #clock-cells = <1>;
438                         };
439
440                         sys_rst: reset {
441                                 compatible = "socionext,uniphier-sld3-reset";
442                                 #reset-cells = <1>;
443                         };
444                 };
445
446                 nand: nand@f8000000 {
447                         compatible = "socionext,denali-nand-v5a";
448                         status = "disabled";
449                         reg-names = "nand_data", "denali_reg";
450                         reg = <0xf8000000 0x20>, <0xf8100000 0x1000>;
451                         interrupts = <0 65 4>;
452                         clocks = <&sys_clk 2>;
453                         nand-ecc-strength = <8>;
454                 };
455         };
456 };
457
458 /include/ "uniphier-pinctrl.dtsi"