git.sur5r.net Git - u-boot/blob - arch/arm/dts/uniphier-sld3.dtsi

   1 /*
   2  * Device Tree Source for UniPhier sLD3 SoC
   3  *
   4  * Copyright (C) 2015-2016 Socionext Inc.
   5  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+        X11
   8  */
   9
  10 /include/ "skeleton.dtsi"
  11
  12 / {
  13         compatible = "socionext,uniphier-sld3";
  14
  15         cpus {
  16                 #address-cells = <1>;
  17                 #size-cells = <0>;
  18
  19                 cpu@0 {
  20                         device_type = "cpu";
  21                         compatible = "arm,cortex-a9";
  22                         reg = <0>;
  23                         enable-method = "psci";
  24                         next-level-cache = <&l2>;
  25                 };
  26
  27                 cpu@1 {
  28                         device_type = "cpu";
  29                         compatible = "arm,cortex-a9";
  30                         reg = <1>;
  31                         enable-method = "psci";
  32                         next-level-cache = <&l2>;
  33                 };
  34         };
  35
  36         psci {
  37                 compatible = "arm,psci-0.2";
  38                 method = "smc";
  39         };
  40
  41         clocks {
  42                 refclk: ref {
  43                         #clock-cells = <0>;
  44                         compatible = "fixed-clock";
  45                         clock-frequency = <24576000>;
  46                 };
  47
  48                 arm_timer_clk: arm_timer_clk {
  49                         #clock-cells = <0>;
  50                         compatible = "fixed-clock";
  51                         clock-frequency = <50000000>;
  52                 };
  53
  54                 iobus_clk: iobus_clk {
  55                         #clock-cells = <0>;
  56                         compatible = "fixed-clock";
  57                         clock-frequency = <100000000>;
  58                 };
  59         };
  60
  61         soc {
  62                 compatible = "simple-bus";
  63                 #address-cells = <1>;
  64                 #size-cells = <1>;
  65                 ranges;
  66                 interrupt-parent = <&intc>;
  67                 u-boot,dm-pre-reloc;
  68
  69                 timer@20000200 {
  70                         compatible = "arm,cortex-a9-global-timer";
  71                         reg = <0x20000200 0x20>;
  72                         interrupts = <1 11 0x304>;
  73                         clocks = <&arm_timer_clk>;
  74                 };
  75
  76                 timer@20000600 {
  77                         compatible = "arm,cortex-a9-twd-timer";
  78                         reg = <0x20000600 0x20>;
  79                         interrupts = <1 13 0x304>;
  80                         clocks = <&arm_timer_clk>;
  81                 };
  82
  83                 intc: interrupt-controller@20001000 {
  84                         compatible = "arm,cortex-a9-gic";
  85                         #interrupt-cells = <3>;
  86                         interrupt-controller;
  87                         reg = <0x20001000 0x1000>,
  88                               <0x20000100 0x100>;
  89                 };
  90
  91                 l2: l2-cache@500c0000 {
  92                         compatible = "socionext,uniphier-system-cache";
  93                         reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
  94                               <0x506c0000 0x400>;
  95                         interrupts = <0 174 4>, <0 175 4>;
  96                         cache-unified;
  97                         cache-size = <(512 * 1024)>;
  98                         cache-sets = <256>;
  99                         cache-line-size = <128>;
 100                         cache-level = <2>;
 101                 };
 102
 103                 serial0: serial@54006800 {
 104                         compatible = "socionext,uniphier-uart";
 105                         status = "disabled";
 106                         reg = <0x54006800 0x40>;
 107                         interrupts = <0 33 4>;
 108                         pinctrl-names = "default";
 109                         pinctrl-0 = <&pinctrl_uart0>;
 110                         clock-frequency = <36864000>;
 111                 };
 112
 113                 serial1: serial@54006900 {
 114                         compatible = "socionext,uniphier-uart";
 115                         status = "disabled";
 116                         reg = <0x54006900 0x40>;
 117                         interrupts = <0 35 4>;
 118                         pinctrl-names = "default";
 119                         pinctrl-0 = <&pinctrl_uart1>;
 120                         clock-frequency = <36864000>;
 121                 };
 122
 123                 serial2: serial@54006a00 {
 124                         compatible = "socionext,uniphier-uart";
 125                         status = "disabled";
 126                         reg = <0x54006a00 0x40>;
 127                         interrupts = <0 37 4>;
 128                         pinctrl-names = "default";
 129                         pinctrl-0 = <&pinctrl_uart2>;
 130                         clock-frequency = <36864000>;
 131                 };
 132
 133                 port0x: gpio@55000008 {
 134                         compatible = "socionext,uniphier-gpio";
 135                         reg = <0x55000008 0x8>;
 136                         gpio-controller;
 137                         #gpio-cells = <2>;
 138                 };
 139
 140                 port1x: gpio@55000010 {
 141                         compatible = "socionext,uniphier-gpio";
 142                         reg = <0x55000010 0x8>;
 143                         gpio-controller;
 144                         #gpio-cells = <2>;
 145                 };
 146
 147                 port2x: gpio@55000018 {
 148                         compatible = "socionext,uniphier-gpio";
 149                         reg = <0x55000018 0x8>;
 150                         gpio-controller;
 151                         #gpio-cells = <2>;
 152                 };
 153
 154                 port3x: gpio@55000020 {
 155                         compatible = "socionext,uniphier-gpio";
 156                         reg = <0x55000020 0x8>;
 157                         gpio-controller;
 158                         #gpio-cells = <2>;
 159                 };
 160
 161                 port4: gpio@55000028 {
 162                         compatible = "socionext,uniphier-gpio";
 163                         reg = <0x55000028 0x8>;
 164                         gpio-controller;
 165                         #gpio-cells = <2>;
 166                 };
 167
 168                 port5x: gpio@55000030 {
 169                         compatible = "socionext,uniphier-gpio";
 170                         reg = <0x55000030 0x8>;
 171                         gpio-controller;
 172                         #gpio-cells = <2>;
 173                 };
 174
 175                 port6x: gpio@55000038 {
 176                         compatible = "socionext,uniphier-gpio";
 177                         reg = <0x55000038 0x8>;
 178                         gpio-controller;
 179                         #gpio-cells = <2>;
 180                 };
 181
 182                 port7x: gpio@55000040 {
 183                         compatible = "socionext,uniphier-gpio";
 184                         reg = <0x55000040 0x8>;
 185                         gpio-controller;
 186                         #gpio-cells = <2>;
 187                 };
 188
 189                 port8x: gpio@55000048 {
 190                         compatible = "socionext,uniphier-gpio";
 191                         reg = <0x55000048 0x8>;
 192                         gpio-controller;
 193                         #gpio-cells = <2>;
 194                 };
 195
 196                 port9x: gpio@55000050 {
 197                         compatible = "socionext,uniphier-gpio";
 198                         reg = <0x55000050 0x8>;
 199                         gpio-controller;
 200                         #gpio-cells = <2>;
 201                 };
 202
 203                 port10x: gpio@55000058 {
 204                         compatible = "socionext,uniphier-gpio";
 205                         reg = <0x55000058 0x8>;
 206                         gpio-controller;
 207                         #gpio-cells = <2>;
 208                 };
 209
 210                 port11x: gpio@55000060 {
 211                         compatible = "socionext,uniphier-gpio";
 212                         reg = <0x55000060 0x8>;
 213                         gpio-controller;
 214                         #gpio-cells = <2>;
 215                 };
 216
 217                 port12x: gpio@55000068 {
 218                         compatible = "socionext,uniphier-gpio";
 219                         reg = <0x55000068 0x8>;
 220                         gpio-controller;
 221                         #gpio-cells = <2>;
 222                 };
 223
 224                 port13x: gpio@55000070 {
 225                         compatible = "socionext,uniphier-gpio";
 226                         reg = <0x55000070 0x8>;
 227                         gpio-controller;
 228                         #gpio-cells = <2>;
 229                 };
 230
 231                 port14x: gpio@55000078 {
 232                         compatible = "socionext,uniphier-gpio";
 233                         reg = <0x55000078 0x8>;
 234                         gpio-controller;
 235                         #gpio-cells = <2>;
 236                 };
 237
 238                 port16x: gpio@55000088 {
 239                         compatible = "socionext,uniphier-gpio";
 240                         reg = <0x55000088 0x8>;
 241                         gpio-controller;
 242                         #gpio-cells = <2>;
 243                 };
 244
 245                 i2c0: i2c@58400000 {
 246                         compatible = "socionext,uniphier-i2c";
 247                         status = "disabled";
 248                         reg = <0x58400000 0x40>;
 249                         #address-cells = <1>;
 250                         #size-cells = <0>;
 251                         interrupts = <0 41 1>;
 252                         pinctrl-names = "default";
 253                         pinctrl-0 = <&pinctrl_i2c0>;
 254                         clocks = <&iobus_clk>;
 255                         clock-frequency = <100000>;
 256                 };
 257
 258                 i2c1: i2c@58480000 {
 259                         compatible = "socionext,uniphier-i2c";
 260                         status = "disabled";
 261                         reg = <0x58480000 0x40>;
 262                         #address-cells = <1>;
 263                         #size-cells = <0>;
 264                         interrupts = <0 42 1>;
 265                         clocks = <&iobus_clk>;
 266                         clock-frequency = <100000>;
 267                 };
 268
 269                 i2c2: i2c@58500000 {
 270                         compatible = "socionext,uniphier-i2c";
 271                         status = "disabled";
 272                         reg = <0x58500000 0x40>;
 273                         #address-cells = <1>;
 274                         #size-cells = <0>;
 275                         interrupts = <0 43 1>;
 276                         clocks = <&iobus_clk>;
 277                         clock-frequency = <100000>;
 278                 };
 279
 280                 i2c3: i2c@58580000 {
 281                         compatible = "socionext,uniphier-i2c";
 282                         status = "disabled";
 283                         reg = <0x58580000 0x40>;
 284                         #address-cells = <1>;
 285                         #size-cells = <0>;
 286                         interrupts = <0 44 1>;
 287                         clocks = <&iobus_clk>;
 288                         clock-frequency = <100000>;
 289                 };
 290
 291                 /* chip-internal connection for DMD */
 292                 i2c4: i2c@58600000 {
 293                         compatible = "socionext,uniphier-i2c";
 294                         reg = <0x58600000 0x40>;
 295                         #address-cells = <1>;
 296                         #size-cells = <0>;
 297                         interrupts = <0 45 1>;
 298                         clocks = <&iobus_clk>;
 299                         clock-frequency = <400000>;
 300                 };
 301
 302                 system_bus: system-bus@58c00000 {
 303                         compatible = "socionext,uniphier-system-bus";
 304                         status = "disabled";
 305                         reg = <0x58c00000 0x400>;
 306                         #address-cells = <2>;
 307                         #size-cells = <1>;
 308                 };
 309
 310                 smpctrl@59800000 {
 311                         compatible = "socionext,uniphier-smpctrl";
 312                         reg = <0x59801000 0x400>;
 313                 };
 314
 315                 mioctrl@59810000 {
 316                         compatible = "socionext,uniphier-mioctrl",
 317                                      "simple-mfd", "syscon";
 318                         reg = <0x59810000 0x800>;
 319                         u-boot,dm-pre-reloc;
 320
 321                         mio_clk: clock {
 322                                 compatible = "socionext,uniphier-sld3-mio-clock";
 323                                 #clock-cells = <1>;
 324                                 u-boot,dm-pre-reloc;
 325                         };
 326
 327                         mio_rst: reset {
 328                                 compatible = "socionext,uniphier-sld3-mio-reset";
 329                                 #reset-cells = <1>;
 330                         };
 331                 };
 332
 333                 emmc: sdhc@5a400000 {
 334                         compatible = "socionext,uniphier-sdhc";
 335                         status = "disabled";
 336                         reg = <0x5a400000 0x200>;
 337                         interrupts = <0 78 4>;
 338                         pinctrl-names = "default", "1.8v";
 339                         pinctrl-0 = <&pinctrl_emmc>;
 340                         pinctrl-1 = <&pinctrl_emmc_1v8>;
 341                         clocks = <&mio_clk 1>;
 342                         resets = <&mio_rst 1>, <&mio_rst 4>;
 343                         bus-width = <8>;
 344                         non-removable;
 345                 };
 346
 347                 sd: sdhc@5a500000 {
 348                         compatible = "socionext,uniphier-sdhc";
 349                         status = "disabled";
 350                         reg = <0x5a500000 0x200>;
 351                         interrupts = <0 76 4>;
 352                         pinctrl-names = "default", "1.8v";
 353                         pinctrl-0 = <&pinctrl_sd>;
 354                         pinctrl-1 = <&pinctrl_sd_1v8>;
 355                         clocks = <&mio_clk 0>;
 356                         resets = <&mio_rst 0>, <&mio_rst 3>;
 357                         bus-width = <4>;
 358                 };
 359
 360                 usb0: usb@5a800100 {
 361                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 362                         status = "disabled";
 363                         reg = <0x5a800100 0x100>;
 364                         interrupts = <0 80 4>;
 365                         pinctrl-names = "default";
 366                         pinctrl-0 = <&pinctrl_usb0>;
 367                         clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
 368                         resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
 369                                  <&mio_rst 12>;
 370                 };
 371
 372                 usb1: usb@5a810100 {
 373                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 374                         status = "disabled";
 375                         reg = <0x5a810100 0x100>;
 376                         interrupts = <0 81 4>;
 377                         pinctrl-names = "default";
 378                         pinctrl-0 = <&pinctrl_usb1>;
 379                         clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
 380                         resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
 381                                  <&mio_rst 13>;
 382                 };
 383
 384                 usb2: usb@5a820100 {
 385                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 386                         status = "disabled";
 387                         reg = <0x5a820100 0x100>;
 388                         interrupts = <0 82 4>;
 389                         pinctrl-names = "default";
 390                         pinctrl-0 = <&pinctrl_usb2>;
 391                         clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>;
 392                         resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
 393                                  <&mio_rst 14>;
 394                 };
 395
 396                 usb3: usb@5a830100 {
 397                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 398                         status = "disabled";
 399                         reg = <0x5a830100 0x100>;
 400                         interrupts = <0 83 4>;
 401                         pinctrl-names = "default";
 402                         pinctrl-0 = <&pinctrl_usb3>;
 403                         clocks = <&mio_clk 7>, <&mio_clk 11>, <&mio_clk 15>;
 404                         resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 11>,
 405                                  <&mio_rst 15>;
 406                 };
 407
 408                 soc-glue@5f800000 {
 409                         compatible = "simple-mfd", "syscon";
 410                         reg = <0x5f800000 0x2000>;
 411                         u-boot,dm-pre-reloc;
 412
 413                         pinctrl: pinctrl {
 414                                 compatible = "socionext,uniphier-sld3-pinctrl";
 415                                 u-boot,dm-pre-reloc;
 416                         };
 417                 };
 418
 419                 aidet@f1830000 {
 420                         compatible = "simple-mfd", "syscon";
 421                         reg = <0xf1830000 0x200>;
 422                 };
 423
 424                 sysctrl@f1840000 {
 425                         compatible = "socionext,uniphier-sysctrl",
 426                                      "simple-mfd", "syscon";
 427                         reg = <0xf1840000 0x4000>;
 428
 429                         sys_clk: clock {
 430                                 compatible = "socionext,uniphier-sld3-clock";
 431                                 #clock-cells = <1>;
 432                         };
 433
 434                         sys_rst: reset {
 435                                 compatible = "socionext,uniphier-sld3-reset";
 436                                 #reset-cells = <1>;
 437                         };
 438                 };
 439
 440                 nand: nand@f8000000 {
 441                         compatible = "denali,denali-nand-dt";
 442                         reg = <0xf8000000 0x20>, <0xf8100000 0x1000>;
 443                         reg-names = "nand_data", "denali_reg";
 444                 };
 445         };
 446 };
 447
 448 /include/ "uniphier-pinctrl.dtsi"