git.sur5r.net Git - u-boot/blob - arch/arm/dts/uniphier-sld3.dtsi

   1 /*
   2  * Device Tree Source for UniPhier sLD3 SoC
   3  *
   4  * Copyright (C) 2015-2016 Socionext Inc.
   5  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+        X11
   8  */
   9
  10 /include/ "skeleton.dtsi"
  11
  12 / {
  13         compatible = "socionext,uniphier-sld3";
  14
  15         cpus {
  16                 #address-cells = <1>;
  17                 #size-cells = <0>;
  18
  19                 cpu@0 {
  20                         device_type = "cpu";
  21                         compatible = "arm,cortex-a9";
  22                         reg = <0>;
  23                         enable-method = "psci";
  24                         next-level-cache = <&l2>;
  25                 };
  26
  27                 cpu@1 {
  28                         device_type = "cpu";
  29                         compatible = "arm,cortex-a9";
  30                         reg = <1>;
  31                         enable-method = "psci";
  32                         next-level-cache = <&l2>;
  33                 };
  34         };
  35
  36         psci {
  37                 compatible = "arm,psci-0.2";
  38                 method = "smc";
  39         };
  40
  41         clocks {
  42                 refclk: ref {
  43                         #clock-cells = <0>;
  44                         compatible = "fixed-clock";
  45                         clock-frequency = <24576000>;
  46                 };
  47
  48                 arm_timer_clk: arm_timer_clk {
  49                         #clock-cells = <0>;
  50                         compatible = "fixed-clock";
  51                         clock-frequency = <50000000>;
  52                 };
  53         };
  54
  55         soc {
  56                 compatible = "simple-bus";
  57                 #address-cells = <1>;
  58                 #size-cells = <1>;
  59                 ranges;
  60                 interrupt-parent = <&intc>;
  61                 u-boot,dm-pre-reloc;
  62
  63                 timer@20000200 {
  64                         compatible = "arm,cortex-a9-global-timer";
  65                         reg = <0x20000200 0x20>;
  66                         interrupts = <1 11 0x304>;
  67                         clocks = <&arm_timer_clk>;
  68                 };
  69
  70                 timer@20000600 {
  71                         compatible = "arm,cortex-a9-twd-timer";
  72                         reg = <0x20000600 0x20>;
  73                         interrupts = <1 13 0x304>;
  74                         clocks = <&arm_timer_clk>;
  75                 };
  76
  77                 intc: interrupt-controller@20001000 {
  78                         compatible = "arm,cortex-a9-gic";
  79                         #interrupt-cells = <3>;
  80                         interrupt-controller;
  81                         reg = <0x20001000 0x1000>,
  82                               <0x20000100 0x100>;
  83                 };
  84
  85                 l2: l2-cache@500c0000 {
  86                         compatible = "socionext,uniphier-system-cache";
  87                         reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
  88                               <0x506c0000 0x400>;
  89                         interrupts = <0 174 4>, <0 175 4>;
  90                         cache-unified;
  91                         cache-size = <(512 * 1024)>;
  92                         cache-sets = <256>;
  93                         cache-line-size = <128>;
  94                         cache-level = <2>;
  95                 };
  96
  97                 serial0: serial@54006800 {
  98                         compatible = "socionext,uniphier-uart";
  99                         status = "disabled";
 100                         reg = <0x54006800 0x40>;
 101                         interrupts = <0 33 4>;
 102                         pinctrl-names = "default";
 103                         pinctrl-0 = <&pinctrl_uart0>;
 104                         clock-frequency = <36864000>;
 105                 };
 106
 107                 serial1: serial@54006900 {
 108                         compatible = "socionext,uniphier-uart";
 109                         status = "disabled";
 110                         reg = <0x54006900 0x40>;
 111                         interrupts = <0 35 4>;
 112                         pinctrl-names = "default";
 113                         pinctrl-0 = <&pinctrl_uart1>;
 114                         clock-frequency = <36864000>;
 115                 };
 116
 117                 serial2: serial@54006a00 {
 118                         compatible = "socionext,uniphier-uart";
 119                         status = "disabled";
 120                         reg = <0x54006a00 0x40>;
 121                         interrupts = <0 37 4>;
 122                         pinctrl-names = "default";
 123                         pinctrl-0 = <&pinctrl_uart2>;
 124                         clock-frequency = <36864000>;
 125                 };
 126
 127                 port0x: gpio@55000008 {
 128                         compatible = "socionext,uniphier-gpio";
 129                         reg = <0x55000008 0x8>;
 130                         gpio-controller;
 131                         #gpio-cells = <2>;
 132                 };
 133
 134                 port1x: gpio@55000010 {
 135                         compatible = "socionext,uniphier-gpio";
 136                         reg = <0x55000010 0x8>;
 137                         gpio-controller;
 138                         #gpio-cells = <2>;
 139                 };
 140
 141                 port2x: gpio@55000018 {
 142                         compatible = "socionext,uniphier-gpio";
 143                         reg = <0x55000018 0x8>;
 144                         gpio-controller;
 145                         #gpio-cells = <2>;
 146                 };
 147
 148                 port3x: gpio@55000020 {
 149                         compatible = "socionext,uniphier-gpio";
 150                         reg = <0x55000020 0x8>;
 151                         gpio-controller;
 152                         #gpio-cells = <2>;
 153                 };
 154
 155                 port4: gpio@55000028 {
 156                         compatible = "socionext,uniphier-gpio";
 157                         reg = <0x55000028 0x8>;
 158                         gpio-controller;
 159                         #gpio-cells = <2>;
 160                 };
 161
 162                 port5x: gpio@55000030 {
 163                         compatible = "socionext,uniphier-gpio";
 164                         reg = <0x55000030 0x8>;
 165                         gpio-controller;
 166                         #gpio-cells = <2>;
 167                 };
 168
 169                 port6x: gpio@55000038 {
 170                         compatible = "socionext,uniphier-gpio";
 171                         reg = <0x55000038 0x8>;
 172                         gpio-controller;
 173                         #gpio-cells = <2>;
 174                 };
 175
 176                 port7x: gpio@55000040 {
 177                         compatible = "socionext,uniphier-gpio";
 178                         reg = <0x55000040 0x8>;
 179                         gpio-controller;
 180                         #gpio-cells = <2>;
 181                 };
 182
 183                 port8x: gpio@55000048 {
 184                         compatible = "socionext,uniphier-gpio";
 185                         reg = <0x55000048 0x8>;
 186                         gpio-controller;
 187                         #gpio-cells = <2>;
 188                 };
 189
 190                 port9x: gpio@55000050 {
 191                         compatible = "socionext,uniphier-gpio";
 192                         reg = <0x55000050 0x8>;
 193                         gpio-controller;
 194                         #gpio-cells = <2>;
 195                 };
 196
 197                 port10x: gpio@55000058 {
 198                         compatible = "socionext,uniphier-gpio";
 199                         reg = <0x55000058 0x8>;
 200                         gpio-controller;
 201                         #gpio-cells = <2>;
 202                 };
 203
 204                 port11x: gpio@55000060 {
 205                         compatible = "socionext,uniphier-gpio";
 206                         reg = <0x55000060 0x8>;
 207                         gpio-controller;
 208                         #gpio-cells = <2>;
 209                 };
 210
 211                 port12x: gpio@55000068 {
 212                         compatible = "socionext,uniphier-gpio";
 213                         reg = <0x55000068 0x8>;
 214                         gpio-controller;
 215                         #gpio-cells = <2>;
 216                 };
 217
 218                 port13x: gpio@55000070 {
 219                         compatible = "socionext,uniphier-gpio";
 220                         reg = <0x55000070 0x8>;
 221                         gpio-controller;
 222                         #gpio-cells = <2>;
 223                 };
 224
 225                 port14x: gpio@55000078 {
 226                         compatible = "socionext,uniphier-gpio";
 227                         reg = <0x55000078 0x8>;
 228                         gpio-controller;
 229                         #gpio-cells = <2>;
 230                 };
 231
 232                 port16x: gpio@55000088 {
 233                         compatible = "socionext,uniphier-gpio";
 234                         reg = <0x55000088 0x8>;
 235                         gpio-controller;
 236                         #gpio-cells = <2>;
 237                 };
 238
 239                 i2c0: i2c@58400000 {
 240                         compatible = "socionext,uniphier-i2c";
 241                         status = "disabled";
 242                         reg = <0x58400000 0x40>;
 243                         #address-cells = <1>;
 244                         #size-cells = <0>;
 245                         interrupts = <0 41 1>;
 246                         pinctrl-names = "default";
 247                         pinctrl-0 = <&pinctrl_i2c0>;
 248                         clocks = <&sys_clk 1>;
 249                         clock-frequency = <100000>;
 250                 };
 251
 252                 i2c1: i2c@58480000 {
 253                         compatible = "socionext,uniphier-i2c";
 254                         status = "disabled";
 255                         reg = <0x58480000 0x40>;
 256                         #address-cells = <1>;
 257                         #size-cells = <0>;
 258                         interrupts = <0 42 1>;
 259                         clocks = <&sys_clk 1>;
 260                         clock-frequency = <100000>;
 261                 };
 262
 263                 i2c2: i2c@58500000 {
 264                         compatible = "socionext,uniphier-i2c";
 265                         status = "disabled";
 266                         reg = <0x58500000 0x40>;
 267                         #address-cells = <1>;
 268                         #size-cells = <0>;
 269                         interrupts = <0 43 1>;
 270                         clocks = <&sys_clk 1>;
 271                         clock-frequency = <100000>;
 272                 };
 273
 274                 i2c3: i2c@58580000 {
 275                         compatible = "socionext,uniphier-i2c";
 276                         status = "disabled";
 277                         reg = <0x58580000 0x40>;
 278                         #address-cells = <1>;
 279                         #size-cells = <0>;
 280                         interrupts = <0 44 1>;
 281                         clocks = <&sys_clk 1>;
 282                         clock-frequency = <100000>;
 283                 };
 284
 285                 /* chip-internal connection for DMD */
 286                 i2c4: i2c@58600000 {
 287                         compatible = "socionext,uniphier-i2c";
 288                         reg = <0x58600000 0x40>;
 289                         #address-cells = <1>;
 290                         #size-cells = <0>;
 291                         interrupts = <0 45 1>;
 292                         clocks = <&sys_clk 1>;
 293                         clock-frequency = <400000>;
 294                 };
 295
 296                 system_bus: system-bus@58c00000 {
 297                         compatible = "socionext,uniphier-system-bus";
 298                         status = "disabled";
 299                         reg = <0x58c00000 0x400>;
 300                         #address-cells = <2>;
 301                         #size-cells = <1>;
 302                 };
 303
 304                 smpctrl@59800000 {
 305                         compatible = "socionext,uniphier-smpctrl";
 306                         reg = <0x59801000 0x400>;
 307                 };
 308
 309                 mioctrl@59810000 {
 310                         compatible = "socionext,uniphier-mioctrl",
 311                                      "simple-mfd", "syscon";
 312                         reg = <0x59810000 0x800>;
 313                         u-boot,dm-pre-reloc;
 314
 315                         mio_clk: clock {
 316                                 compatible = "socionext,uniphier-sld3-mio-clock";
 317                                 #clock-cells = <1>;
 318                                 u-boot,dm-pre-reloc;
 319                         };
 320
 321                         mio_rst: reset {
 322                                 compatible = "socionext,uniphier-sld3-mio-reset";
 323                                 #reset-cells = <1>;
 324                         };
 325                 };
 326
 327                 emmc: sdhc@5a400000 {
 328                         compatible = "socionext,uniphier-sdhc";
 329                         status = "disabled";
 330                         reg = <0x5a400000 0x200>;
 331                         interrupts = <0 78 4>;
 332                         pinctrl-names = "default", "1.8v";
 333                         pinctrl-0 = <&pinctrl_emmc>;
 334                         pinctrl-1 = <&pinctrl_emmc_1v8>;
 335                         clocks = <&mio_clk 1>;
 336                         reset-names = "host", "bridge";
 337                         resets = <&mio_rst 1>, <&mio_rst 4>;
 338                         bus-width = <8>;
 339                         non-removable;
 340                         cap-mmc-highspeed;
 341                         cap-mmc-hw-reset;
 342                 };
 343
 344                 sd: sdhc@5a500000 {
 345                         compatible = "socionext,uniphier-sdhc";
 346                         status = "disabled";
 347                         reg = <0x5a500000 0x200>;
 348                         interrupts = <0 76 4>;
 349                         pinctrl-names = "default", "1.8v";
 350                         pinctrl-0 = <&pinctrl_sd>;
 351                         pinctrl-1 = <&pinctrl_sd_1v8>;
 352                         clocks = <&mio_clk 0>;
 353                         reset-names = "host", "bridge";
 354                         resets = <&mio_rst 0>, <&mio_rst 3>;
 355                         bus-width = <4>;
 356                         cap-sd-highspeed;
 357                         sd-uhs-sdr12;
 358                         sd-uhs-sdr25;
 359                         sd-uhs-sdr50;
 360                 };
 361
 362                 usb0: usb@5a800100 {
 363                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 364                         status = "disabled";
 365                         reg = <0x5a800100 0x100>;
 366                         interrupts = <0 80 4>;
 367                         pinctrl-names = "default";
 368                         pinctrl-0 = <&pinctrl_usb0>;
 369                         clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
 370                         resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
 371                                  <&mio_rst 12>;
 372                 };
 373
 374                 usb1: usb@5a810100 {
 375                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 376                         status = "disabled";
 377                         reg = <0x5a810100 0x100>;
 378                         interrupts = <0 81 4>;
 379                         pinctrl-names = "default";
 380                         pinctrl-0 = <&pinctrl_usb1>;
 381                         clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
 382                         resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
 383                                  <&mio_rst 13>;
 384                 };
 385
 386                 usb2: usb@5a820100 {
 387                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 388                         status = "disabled";
 389                         reg = <0x5a820100 0x100>;
 390                         interrupts = <0 82 4>;
 391                         pinctrl-names = "default";
 392                         pinctrl-0 = <&pinctrl_usb2>;
 393                         clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>;
 394                         resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
 395                                  <&mio_rst 14>;
 396                 };
 397
 398                 usb3: usb@5a830100 {
 399                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 400                         status = "disabled";
 401                         reg = <0x5a830100 0x100>;
 402                         interrupts = <0 83 4>;
 403                         pinctrl-names = "default";
 404                         pinctrl-0 = <&pinctrl_usb3>;
 405                         clocks = <&mio_clk 7>, <&mio_clk 11>, <&mio_clk 15>;
 406                         resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 11>,
 407                                  <&mio_rst 15>;
 408                 };
 409
 410                 soc-glue@5f800000 {
 411                         compatible = "socionext,uniphier-sld3-soc-glue",
 412                                      "simple-mfd", "syscon";
 413                         reg = <0x5f800000 0x2000>;
 414                         u-boot,dm-pre-reloc;
 415
 416                         pinctrl: pinctrl {
 417                                 compatible = "socionext,uniphier-sld3-pinctrl";
 418                                 u-boot,dm-pre-reloc;
 419                         };
 420                 };
 421
 422                 aidet@f1830000 {
 423                         compatible = "simple-mfd", "syscon";
 424                         reg = <0xf1830000 0x200>;
 425                 };
 426
 427                 sysctrl@f1840000 {
 428                         compatible = "socionext,uniphier-sld3-sysctrl",
 429                                      "simple-mfd", "syscon";
 430                         reg = <0xf1840000 0x4000>;
 431
 432                         sys_clk: clock {
 433                                 compatible = "socionext,uniphier-sld3-clock";
 434                                 #clock-cells = <1>;
 435                         };
 436
 437                         sys_rst: reset {
 438                                 compatible = "socionext,uniphier-sld3-reset";
 439                                 #reset-cells = <1>;
 440                         };
 441                 };
 442
 443                 nand: nand@f8000000 {
 444                         compatible = "socionext,denali-nand-v5a";
 445                         status = "disabled";
 446                         reg-names = "nand_data", "denali_reg";
 447                         reg = <0xf8000000 0x20>, <0xf8100000 0x1000>;
 448                         interrupts = <0 65 4>;
 449                         clocks = <&sys_clk 2>;
 450                         nand-ecc-strength = <8>;
 451                 };
 452         };
 453 };
 454
 455 /include/ "uniphier-pinctrl.dtsi"