2 * Device Tree Source for UniPhier sLD3 SoC
4 * Copyright (C) 2015-2016 Socionext Inc.
5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
7 * SPDX-License-Identifier: GPL-2.0+ X11
11 compatible = "socionext,uniphier-sld3";
21 compatible = "arm,cortex-a9";
23 enable-method = "psci";
24 next-level-cache = <&l2>;
29 compatible = "arm,cortex-a9";
31 enable-method = "psci";
32 next-level-cache = <&l2>;
37 compatible = "arm,psci-0.2";
44 compatible = "fixed-clock";
45 clock-frequency = <24576000>;
48 arm_timer_clk: arm_timer_clk {
50 compatible = "fixed-clock";
51 clock-frequency = <50000000>;
56 compatible = "simple-bus";
60 interrupt-parent = <&intc>;
64 compatible = "arm,cortex-a9-global-timer";
65 reg = <0x20000200 0x20>;
66 interrupts = <1 11 0x304>;
67 clocks = <&arm_timer_clk>;
71 compatible = "arm,cortex-a9-twd-timer";
72 reg = <0x20000600 0x20>;
73 interrupts = <1 13 0x304>;
74 clocks = <&arm_timer_clk>;
77 intc: interrupt-controller@20001000 {
78 compatible = "arm,cortex-a9-gic";
79 #interrupt-cells = <3>;
81 reg = <0x20001000 0x1000>,
85 l2: l2-cache@500c0000 {
86 compatible = "socionext,uniphier-system-cache";
87 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
89 interrupts = <0 174 4>, <0 175 4>;
91 cache-size = <(512 * 1024)>;
93 cache-line-size = <128>;
97 serial0: serial@54006800 {
98 compatible = "socionext,uniphier-uart";
100 reg = <0x54006800 0x40>;
101 interrupts = <0 33 4>;
102 pinctrl-names = "default";
103 pinctrl-0 = <&pinctrl_uart0>;
104 clock-frequency = <36864000>;
107 serial1: serial@54006900 {
108 compatible = "socionext,uniphier-uart";
110 reg = <0x54006900 0x40>;
111 interrupts = <0 35 4>;
112 pinctrl-names = "default";
113 pinctrl-0 = <&pinctrl_uart1>;
114 clock-frequency = <36864000>;
117 serial2: serial@54006a00 {
118 compatible = "socionext,uniphier-uart";
120 reg = <0x54006a00 0x40>;
121 interrupts = <0 37 4>;
122 pinctrl-names = "default";
123 pinctrl-0 = <&pinctrl_uart2>;
124 clock-frequency = <36864000>;
127 port0x: gpio@55000008 {
128 compatible = "socionext,uniphier-gpio";
129 reg = <0x55000008 0x8>;
134 port1x: gpio@55000010 {
135 compatible = "socionext,uniphier-gpio";
136 reg = <0x55000010 0x8>;
141 port2x: gpio@55000018 {
142 compatible = "socionext,uniphier-gpio";
143 reg = <0x55000018 0x8>;
148 port3x: gpio@55000020 {
149 compatible = "socionext,uniphier-gpio";
150 reg = <0x55000020 0x8>;
155 port4: gpio@55000028 {
156 compatible = "socionext,uniphier-gpio";
157 reg = <0x55000028 0x8>;
162 port5x: gpio@55000030 {
163 compatible = "socionext,uniphier-gpio";
164 reg = <0x55000030 0x8>;
169 port6x: gpio@55000038 {
170 compatible = "socionext,uniphier-gpio";
171 reg = <0x55000038 0x8>;
176 port7x: gpio@55000040 {
177 compatible = "socionext,uniphier-gpio";
178 reg = <0x55000040 0x8>;
183 port8x: gpio@55000048 {
184 compatible = "socionext,uniphier-gpio";
185 reg = <0x55000048 0x8>;
190 port9x: gpio@55000050 {
191 compatible = "socionext,uniphier-gpio";
192 reg = <0x55000050 0x8>;
197 port10x: gpio@55000058 {
198 compatible = "socionext,uniphier-gpio";
199 reg = <0x55000058 0x8>;
204 port11x: gpio@55000060 {
205 compatible = "socionext,uniphier-gpio";
206 reg = <0x55000060 0x8>;
211 port12x: gpio@55000068 {
212 compatible = "socionext,uniphier-gpio";
213 reg = <0x55000068 0x8>;
218 port13x: gpio@55000070 {
219 compatible = "socionext,uniphier-gpio";
220 reg = <0x55000070 0x8>;
225 port14x: gpio@55000078 {
226 compatible = "socionext,uniphier-gpio";
227 reg = <0x55000078 0x8>;
232 port16x: gpio@55000088 {
233 compatible = "socionext,uniphier-gpio";
234 reg = <0x55000088 0x8>;
240 compatible = "socionext,uniphier-i2c";
242 reg = <0x58400000 0x40>;
243 #address-cells = <1>;
245 interrupts = <0 41 1>;
246 pinctrl-names = "default";
247 pinctrl-0 = <&pinctrl_i2c0>;
248 clocks = <&sys_clk 1>;
249 clock-frequency = <100000>;
253 compatible = "socionext,uniphier-i2c";
255 reg = <0x58480000 0x40>;
256 #address-cells = <1>;
258 interrupts = <0 42 1>;
259 clocks = <&sys_clk 1>;
260 clock-frequency = <100000>;
264 compatible = "socionext,uniphier-i2c";
266 reg = <0x58500000 0x40>;
267 #address-cells = <1>;
269 interrupts = <0 43 1>;
270 clocks = <&sys_clk 1>;
271 clock-frequency = <100000>;
275 compatible = "socionext,uniphier-i2c";
277 reg = <0x58580000 0x40>;
278 #address-cells = <1>;
280 interrupts = <0 44 1>;
281 clocks = <&sys_clk 1>;
282 clock-frequency = <100000>;
285 /* chip-internal connection for DMD */
287 compatible = "socionext,uniphier-i2c";
288 reg = <0x58600000 0x40>;
289 #address-cells = <1>;
291 interrupts = <0 45 1>;
292 clocks = <&sys_clk 1>;
293 clock-frequency = <400000>;
296 system_bus: system-bus@58c00000 {
297 compatible = "socionext,uniphier-system-bus";
299 reg = <0x58c00000 0x400>;
300 #address-cells = <2>;
305 compatible = "socionext,uniphier-smpctrl";
306 reg = <0x59801000 0x400>;
310 compatible = "socionext,uniphier-mioctrl",
311 "simple-mfd", "syscon";
312 reg = <0x59810000 0x800>;
316 compatible = "socionext,uniphier-sld3-mio-clock";
322 compatible = "socionext,uniphier-sld3-mio-reset";
327 emmc: sdhc@5a400000 {
328 compatible = "socionext,uniphier-sdhc";
330 reg = <0x5a400000 0x200>;
331 interrupts = <0 78 4>;
332 pinctrl-names = "default", "1.8v";
333 pinctrl-0 = <&pinctrl_emmc>;
334 pinctrl-1 = <&pinctrl_emmc_1v8>;
335 clocks = <&mio_clk 1>;
336 reset-names = "host", "bridge";
337 resets = <&mio_rst 1>, <&mio_rst 4>;
345 compatible = "socionext,uniphier-sdhc";
347 reg = <0x5a500000 0x200>;
348 interrupts = <0 76 4>;
349 pinctrl-names = "default", "1.8v";
350 pinctrl-0 = <&pinctrl_sd>;
351 pinctrl-1 = <&pinctrl_sd_1v8>;
352 clocks = <&mio_clk 0>;
353 reset-names = "host", "bridge";
354 resets = <&mio_rst 0>, <&mio_rst 3>;
363 compatible = "socionext,uniphier-ehci", "generic-ehci";
365 reg = <0x5a800100 0x100>;
366 interrupts = <0 80 4>;
367 pinctrl-names = "default";
368 pinctrl-0 = <&pinctrl_usb0>;
369 clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
370 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
375 compatible = "socionext,uniphier-ehci", "generic-ehci";
377 reg = <0x5a810100 0x100>;
378 interrupts = <0 81 4>;
379 pinctrl-names = "default";
380 pinctrl-0 = <&pinctrl_usb1>;
381 clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
382 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
387 compatible = "socionext,uniphier-ehci", "generic-ehci";
389 reg = <0x5a820100 0x100>;
390 interrupts = <0 82 4>;
391 pinctrl-names = "default";
392 pinctrl-0 = <&pinctrl_usb2>;
393 clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>;
394 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
399 compatible = "socionext,uniphier-ehci", "generic-ehci";
401 reg = <0x5a830100 0x100>;
402 interrupts = <0 83 4>;
403 pinctrl-names = "default";
404 pinctrl-0 = <&pinctrl_usb3>;
405 clocks = <&mio_clk 7>, <&mio_clk 11>, <&mio_clk 15>;
406 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 11>,
411 compatible = "socionext,uniphier-sld3-soc-glue",
412 "simple-mfd", "syscon";
413 reg = <0x5f800000 0x2000>;
417 compatible = "socionext,uniphier-sld3-pinctrl";
423 compatible = "simple-mfd", "syscon";
424 reg = <0xf1830000 0x200>;
428 compatible = "socionext,uniphier-sld3-sysctrl",
429 "simple-mfd", "syscon";
430 reg = <0xf1840000 0x4000>;
433 compatible = "socionext,uniphier-sld3-clock";
438 compatible = "socionext,uniphier-sld3-reset";
443 nand: nand@f8000000 {
444 compatible = "socionext,denali-nand-v5a";
446 reg-names = "nand_data", "denali_reg";
447 reg = <0xf8000000 0x20>, <0xf8100000 0x1000>;
448 interrupts = <0 65 4>;
449 clocks = <&sys_clk 2>;
450 nand-ecc-strength = <8>;
455 /include/ "uniphier-pinctrl.dtsi"