2 * Device Tree Source for UniPhier sLD3 SoC
4 * Copyright (C) 2015-2016 Socionext Inc.
5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
7 * This file is dual-licensed: you can use it either under the terms
8 * of the GPL or the X11 license, at your option. Note that this dual
9 * licensing only applies to this file, and not this project as a
12 * a) This file is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of the
15 * License, or (at your option) any later version.
17 * This file is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
24 * b) Permission is hereby granted, free of charge, to any person
25 * obtaining a copy of this software and associated documentation
26 * files (the "Software"), to deal in the Software without
27 * restriction, including without limitation the rights to use,
28 * copy, modify, merge, publish, distribute, sublicense, and/or
29 * sell copies of the Software, and to permit persons to whom the
30 * Software is furnished to do so, subject to the following
33 * The above copyright notice and this permission notice shall be
34 * included in all copies or substantial portions of the Software.
36 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
37 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
38 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
39 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
40 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
41 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
42 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
43 * OTHER DEALINGS IN THE SOFTWARE.
47 compatible = "socionext,uniphier-sld3";
57 compatible = "arm,cortex-a9";
59 enable-method = "psci";
60 next-level-cache = <&l2>;
65 compatible = "arm,cortex-a9";
67 enable-method = "psci";
68 next-level-cache = <&l2>;
73 compatible = "arm,psci-0.2";
80 compatible = "fixed-clock";
81 clock-frequency = <24576000>;
84 arm_timer_clk: arm_timer_clk {
86 compatible = "fixed-clock";
87 clock-frequency = <50000000>;
92 compatible = "simple-bus";
96 interrupt-parent = <&intc>;
100 compatible = "arm,cortex-a9-global-timer";
101 reg = <0x20000200 0x20>;
102 interrupts = <1 11 0x304>;
103 clocks = <&arm_timer_clk>;
107 compatible = "arm,cortex-a9-twd-timer";
108 reg = <0x20000600 0x20>;
109 interrupts = <1 13 0x304>;
110 clocks = <&arm_timer_clk>;
113 intc: interrupt-controller@20001000 {
114 compatible = "arm,cortex-a9-gic";
115 #interrupt-cells = <3>;
116 interrupt-controller;
117 reg = <0x20001000 0x1000>,
121 l2: l2-cache@500c0000 {
122 compatible = "socionext,uniphier-system-cache";
123 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
125 interrupts = <0 174 4>, <0 175 4>;
127 cache-size = <(512 * 1024)>;
129 cache-line-size = <128>;
133 serial0: serial@54006800 {
134 compatible = "socionext,uniphier-uart";
136 reg = <0x54006800 0x40>;
137 interrupts = <0 33 4>;
138 pinctrl-names = "default";
139 pinctrl-0 = <&pinctrl_uart0>;
140 clocks = <&sys_clk 0>;
141 clock-frequency = <36864000>;
144 serial1: serial@54006900 {
145 compatible = "socionext,uniphier-uart";
147 reg = <0x54006900 0x40>;
148 interrupts = <0 35 4>;
149 pinctrl-names = "default";
150 pinctrl-0 = <&pinctrl_uart1>;
151 clocks = <&sys_clk 0>;
152 clock-frequency = <36864000>;
155 serial2: serial@54006a00 {
156 compatible = "socionext,uniphier-uart";
158 reg = <0x54006a00 0x40>;
159 interrupts = <0 37 4>;
160 pinctrl-names = "default";
161 pinctrl-0 = <&pinctrl_uart2>;
162 clocks = <&sys_clk 0>;
163 clock-frequency = <36864000>;
166 port0x: gpio@55000008 {
167 compatible = "socionext,uniphier-gpio";
168 reg = <0x55000008 0x8>;
173 port1x: gpio@55000010 {
174 compatible = "socionext,uniphier-gpio";
175 reg = <0x55000010 0x8>;
180 port2x: gpio@55000018 {
181 compatible = "socionext,uniphier-gpio";
182 reg = <0x55000018 0x8>;
187 port3x: gpio@55000020 {
188 compatible = "socionext,uniphier-gpio";
189 reg = <0x55000020 0x8>;
194 port4: gpio@55000028 {
195 compatible = "socionext,uniphier-gpio";
196 reg = <0x55000028 0x8>;
201 port5x: gpio@55000030 {
202 compatible = "socionext,uniphier-gpio";
203 reg = <0x55000030 0x8>;
208 port6x: gpio@55000038 {
209 compatible = "socionext,uniphier-gpio";
210 reg = <0x55000038 0x8>;
215 port7x: gpio@55000040 {
216 compatible = "socionext,uniphier-gpio";
217 reg = <0x55000040 0x8>;
222 port8x: gpio@55000048 {
223 compatible = "socionext,uniphier-gpio";
224 reg = <0x55000048 0x8>;
229 port9x: gpio@55000050 {
230 compatible = "socionext,uniphier-gpio";
231 reg = <0x55000050 0x8>;
236 port10x: gpio@55000058 {
237 compatible = "socionext,uniphier-gpio";
238 reg = <0x55000058 0x8>;
243 port11x: gpio@55000060 {
244 compatible = "socionext,uniphier-gpio";
245 reg = <0x55000060 0x8>;
250 port12x: gpio@55000068 {
251 compatible = "socionext,uniphier-gpio";
252 reg = <0x55000068 0x8>;
257 port13x: gpio@55000070 {
258 compatible = "socionext,uniphier-gpio";
259 reg = <0x55000070 0x8>;
264 port14x: gpio@55000078 {
265 compatible = "socionext,uniphier-gpio";
266 reg = <0x55000078 0x8>;
271 port16x: gpio@55000088 {
272 compatible = "socionext,uniphier-gpio";
273 reg = <0x55000088 0x8>;
279 compatible = "socionext,uniphier-i2c";
281 reg = <0x58400000 0x40>;
282 #address-cells = <1>;
284 interrupts = <0 41 1>;
285 pinctrl-names = "default";
286 pinctrl-0 = <&pinctrl_i2c0>;
287 clocks = <&sys_clk 1>;
288 clock-frequency = <100000>;
292 compatible = "socionext,uniphier-i2c";
294 reg = <0x58480000 0x40>;
295 #address-cells = <1>;
297 interrupts = <0 42 1>;
298 clocks = <&sys_clk 1>;
299 clock-frequency = <100000>;
303 compatible = "socionext,uniphier-i2c";
305 reg = <0x58500000 0x40>;
306 #address-cells = <1>;
308 interrupts = <0 43 1>;
309 clocks = <&sys_clk 1>;
310 clock-frequency = <100000>;
314 compatible = "socionext,uniphier-i2c";
316 reg = <0x58580000 0x40>;
317 #address-cells = <1>;
319 interrupts = <0 44 1>;
320 clocks = <&sys_clk 1>;
321 clock-frequency = <100000>;
324 /* chip-internal connection for DMD */
326 compatible = "socionext,uniphier-i2c";
327 reg = <0x58600000 0x40>;
328 #address-cells = <1>;
330 interrupts = <0 45 1>;
331 clocks = <&sys_clk 1>;
332 clock-frequency = <400000>;
335 system_bus: system-bus@58c00000 {
336 compatible = "socionext,uniphier-system-bus";
338 reg = <0x58c00000 0x400>;
339 #address-cells = <2>;
344 compatible = "socionext,uniphier-smpctrl";
345 reg = <0x59801000 0x400>;
349 compatible = "socionext,uniphier-sld3-mioctrl",
350 "simple-mfd", "syscon";
351 reg = <0x59810000 0x800>;
355 compatible = "socionext,uniphier-sld3-mio-clock";
361 compatible = "socionext,uniphier-sld3-mio-reset";
366 emmc: sdhc@5a400000 {
367 compatible = "socionext,uniphier-sdhc";
369 reg = <0x5a400000 0x200>;
370 interrupts = <0 78 4>;
371 pinctrl-names = "default", "1.8v";
372 pinctrl-0 = <&pinctrl_emmc>;
373 pinctrl-1 = <&pinctrl_emmc_1v8>;
374 clocks = <&mio_clk 1>;
375 reset-names = "host", "bridge";
376 resets = <&mio_rst 1>, <&mio_rst 4>;
384 compatible = "socionext,uniphier-sdhc";
386 reg = <0x5a500000 0x200>;
387 interrupts = <0 76 4>;
388 pinctrl-names = "default", "1.8v";
389 pinctrl-0 = <&pinctrl_sd>;
390 pinctrl-1 = <&pinctrl_sd_1v8>;
391 clocks = <&mio_clk 0>;
392 reset-names = "host", "bridge";
393 resets = <&mio_rst 0>, <&mio_rst 3>;
402 compatible = "socionext,uniphier-ehci", "generic-ehci";
404 reg = <0x5a800100 0x100>;
405 interrupts = <0 80 4>;
406 pinctrl-names = "default";
407 pinctrl-0 = <&pinctrl_usb0>;
408 clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
409 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
414 compatible = "socionext,uniphier-ehci", "generic-ehci";
416 reg = <0x5a810100 0x100>;
417 interrupts = <0 81 4>;
418 pinctrl-names = "default";
419 pinctrl-0 = <&pinctrl_usb1>;
420 clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
421 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
426 compatible = "socionext,uniphier-ehci", "generic-ehci";
428 reg = <0x5a820100 0x100>;
429 interrupts = <0 82 4>;
430 pinctrl-names = "default";
431 pinctrl-0 = <&pinctrl_usb2>;
432 clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>;
433 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
438 compatible = "socionext,uniphier-ehci", "generic-ehci";
440 reg = <0x5a830100 0x100>;
441 interrupts = <0 83 4>;
442 pinctrl-names = "default";
443 pinctrl-0 = <&pinctrl_usb3>;
444 clocks = <&mio_clk 7>, <&mio_clk 11>, <&mio_clk 15>;
445 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 11>,
450 compatible = "socionext,uniphier-sld3-soc-glue",
451 "simple-mfd", "syscon";
452 reg = <0x5f800000 0x2000>;
456 compatible = "socionext,uniphier-sld3-pinctrl";
462 compatible = "simple-mfd", "syscon";
463 reg = <0xf1830000 0x200>;
467 compatible = "socionext,uniphier-sld3-sysctrl",
468 "simple-mfd", "syscon";
469 reg = <0xf1840000 0x10000>;
472 compatible = "socionext,uniphier-sld3-clock";
477 compatible = "socionext,uniphier-sld3-reset";
482 nand: nand@f8000000 {
483 compatible = "socionext,uniphier-denali-nand-v5a";
485 reg-names = "nand_data", "denali_reg";
486 reg = <0xf8000000 0x20>, <0xf8100000 0x1000>;
487 interrupts = <0 65 4>;
488 clocks = <&sys_clk 2>;
489 nand-ecc-strength = <8>;
494 /include/ "uniphier-pinctrl.dtsi"