1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Device Tree Source for UniPhier sLD8 SoC
5 // Copyright (C) 2015-2016 Socionext Inc.
6 // Author: Masahiro Yamada <yamada.masahiro@socionext.com>
8 #include <dt-bindings/gpio/uniphier-gpio.h>
11 compatible = "socionext,uniphier-sld8";
21 compatible = "arm,cortex-a9";
23 enable-method = "psci";
24 next-level-cache = <&l2>;
29 compatible = "arm,psci-0.2";
35 compatible = "fixed-clock";
37 clock-frequency = <25000000>;
40 arm_timer_clk: arm-timer {
42 compatible = "fixed-clock";
43 clock-frequency = <50000000>;
48 compatible = "simple-bus";
52 interrupt-parent = <&intc>;
54 l2: l2-cache@500c0000 {
55 compatible = "socionext,uniphier-system-cache";
56 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
58 interrupts = <0 174 4>, <0 175 4>;
60 cache-size = <(256 * 1024)>;
62 cache-line-size = <128>;
66 serial0: serial@54006800 {
67 compatible = "socionext,uniphier-uart";
69 reg = <0x54006800 0x40>;
70 interrupts = <0 33 4>;
71 pinctrl-names = "default";
72 pinctrl-0 = <&pinctrl_uart0>;
73 clocks = <&peri_clk 0>;
74 clock-frequency = <80000000>;
75 resets = <&peri_rst 0>;
78 serial1: serial@54006900 {
79 compatible = "socionext,uniphier-uart";
81 reg = <0x54006900 0x40>;
82 interrupts = <0 35 4>;
83 pinctrl-names = "default";
84 pinctrl-0 = <&pinctrl_uart1>;
85 clocks = <&peri_clk 1>;
86 clock-frequency = <80000000>;
87 resets = <&peri_rst 1>;
90 serial2: serial@54006a00 {
91 compatible = "socionext,uniphier-uart";
93 reg = <0x54006a00 0x40>;
94 interrupts = <0 37 4>;
95 pinctrl-names = "default";
96 pinctrl-0 = <&pinctrl_uart2>;
97 clocks = <&peri_clk 2>;
98 clock-frequency = <80000000>;
99 resets = <&peri_rst 2>;
102 serial3: serial@54006b00 {
103 compatible = "socionext,uniphier-uart";
105 reg = <0x54006b00 0x40>;
106 interrupts = <0 29 4>;
107 pinctrl-names = "default";
108 pinctrl-0 = <&pinctrl_uart3>;
109 clocks = <&peri_clk 3>;
110 clock-frequency = <80000000>;
111 resets = <&peri_rst 3>;
114 gpio: gpio@55000000 {
115 compatible = "socionext,uniphier-gpio";
116 reg = <0x55000000 0x200>;
117 interrupt-parent = <&aidet>;
118 interrupt-controller;
119 #interrupt-cells = <2>;
122 gpio-ranges = <&pinctrl 0 0 0>,
125 gpio-ranges-group-names = "gpio_range0",
129 socionext,interrupt-ranges = <0 48 13>, <14 62 2>;
133 compatible = "socionext,uniphier-i2c";
135 reg = <0x58400000 0x40>;
136 #address-cells = <1>;
138 interrupts = <0 41 1>;
139 pinctrl-names = "default";
140 pinctrl-0 = <&pinctrl_i2c0>;
141 clocks = <&peri_clk 4>;
142 resets = <&peri_rst 4>;
143 clock-frequency = <100000>;
147 compatible = "socionext,uniphier-i2c";
149 reg = <0x58480000 0x40>;
150 #address-cells = <1>;
152 interrupts = <0 42 1>;
153 pinctrl-names = "default";
154 pinctrl-0 = <&pinctrl_i2c1>;
155 clocks = <&peri_clk 5>;
156 resets = <&peri_rst 5>;
157 clock-frequency = <100000>;
160 /* chip-internal connection for DMD */
162 compatible = "socionext,uniphier-i2c";
163 reg = <0x58500000 0x40>;
164 #address-cells = <1>;
166 interrupts = <0 43 1>;
167 pinctrl-names = "default";
168 pinctrl-0 = <&pinctrl_i2c2>;
169 clocks = <&peri_clk 6>;
170 resets = <&peri_rst 6>;
171 clock-frequency = <400000>;
175 compatible = "socionext,uniphier-i2c";
177 reg = <0x58580000 0x40>;
178 #address-cells = <1>;
180 interrupts = <0 44 1>;
181 pinctrl-names = "default";
182 pinctrl-0 = <&pinctrl_i2c3>;
183 clocks = <&peri_clk 7>;
184 resets = <&peri_rst 7>;
185 clock-frequency = <100000>;
188 system_bus: system-bus@58c00000 {
189 compatible = "socionext,uniphier-system-bus";
191 reg = <0x58c00000 0x400>;
192 #address-cells = <2>;
194 pinctrl-names = "default";
195 pinctrl-0 = <&pinctrl_system_bus>;
199 compatible = "socionext,uniphier-smpctrl";
200 reg = <0x59801000 0x400>;
204 compatible = "socionext,uniphier-sld8-mioctrl",
205 "simple-mfd", "syscon";
206 reg = <0x59810000 0x800>;
209 compatible = "socionext,uniphier-sld8-mio-clock";
214 compatible = "socionext,uniphier-sld8-mio-reset";
220 compatible = "socionext,uniphier-sld8-perictrl",
221 "simple-mfd", "syscon";
222 reg = <0x59820000 0x200>;
225 compatible = "socionext,uniphier-sld8-peri-clock";
230 compatible = "socionext,uniphier-sld8-peri-reset";
236 compatible = "socionext,uniphier-sdhc";
238 reg = <0x5a400000 0x200>;
239 interrupts = <0 76 4>;
240 pinctrl-names = "default", "1.8v";
241 pinctrl-0 = <&pinctrl_sd>;
242 pinctrl-1 = <&pinctrl_sd_1v8>;
243 clocks = <&mio_clk 0>;
244 reset-names = "host", "bridge";
245 resets = <&mio_rst 0>, <&mio_rst 3>;
253 emmc: sdhc@5a500000 {
254 compatible = "socionext,uniphier-sdhc";
256 reg = <0x5a500000 0x200>;
257 interrupts = <0 78 4>;
258 pinctrl-names = "default", "1.8v";
259 pinctrl-0 = <&pinctrl_emmc>;
260 pinctrl-1 = <&pinctrl_emmc_1v8>;
261 clocks = <&mio_clk 1>;
262 reset-names = "host", "bridge";
263 resets = <&mio_rst 1>, <&mio_rst 4>;
271 compatible = "socionext,uniphier-ehci", "generic-ehci";
273 reg = <0x5a800100 0x100>;
274 interrupts = <0 80 4>;
275 pinctrl-names = "default";
276 pinctrl-0 = <&pinctrl_usb0>;
277 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>,
279 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
281 has-transaction-translator;
285 compatible = "socionext,uniphier-ehci", "generic-ehci";
287 reg = <0x5a810100 0x100>;
288 interrupts = <0 81 4>;
289 pinctrl-names = "default";
290 pinctrl-0 = <&pinctrl_usb1>;
291 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>,
293 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
295 has-transaction-translator;
299 compatible = "socionext,uniphier-ehci", "generic-ehci";
301 reg = <0x5a820100 0x100>;
302 interrupts = <0 82 4>;
303 pinctrl-names = "default";
304 pinctrl-0 = <&pinctrl_usb2>;
305 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 10>,
307 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
309 has-transaction-translator;
313 compatible = "socionext,uniphier-sld8-soc-glue",
314 "simple-mfd", "syscon";
315 reg = <0x5f800000 0x2000>;
318 compatible = "socionext,uniphier-sld8-pinctrl";
323 compatible = "socionext,uniphier-sld8-soc-glue-debug",
325 #address-cells = <1>;
327 ranges = <0 0x5f900000 0x2000>;
330 compatible = "socionext,uniphier-efuse";
335 compatible = "socionext,uniphier-efuse";
341 compatible = "arm,cortex-a9-global-timer";
342 reg = <0x60000200 0x20>;
343 interrupts = <1 11 0x104>;
344 clocks = <&arm_timer_clk>;
348 compatible = "arm,cortex-a9-twd-timer";
349 reg = <0x60000600 0x20>;
350 interrupts = <1 13 0x104>;
351 clocks = <&arm_timer_clk>;
354 intc: interrupt-controller@60001000 {
355 compatible = "arm,cortex-a9-gic";
356 reg = <0x60001000 0x1000>,
358 #interrupt-cells = <3>;
359 interrupt-controller;
362 aidet: aidet@61830000 {
363 compatible = "socionext,uniphier-sld8-aidet";
364 reg = <0x61830000 0x200>;
365 interrupt-controller;
366 #interrupt-cells = <2>;
370 compatible = "socionext,uniphier-sld8-sysctrl",
371 "simple-mfd", "syscon";
372 reg = <0x61840000 0x10000>;
375 compatible = "socionext,uniphier-sld8-clock";
380 compatible = "socionext,uniphier-sld8-reset";
385 nand: nand@68000000 {
386 compatible = "socionext,uniphier-denali-nand-v5a";
388 reg-names = "nand_data", "denali_reg";
389 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
390 interrupts = <0 65 4>;
391 pinctrl-names = "default";
392 pinctrl-0 = <&pinctrl_nand2cs>;
393 clocks = <&sys_clk 2>;
394 resets = <&sys_rst 2>;
399 #include "uniphier-pinctrl.dtsi"