2 * Device Tree Source for UniPhier sLD8 SoC
4 * Copyright (C) 2015-2016 Socionext Inc.
5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
7 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 compatible = "socionext,uniphier-sld8";
21 compatible = "arm,cortex-a9";
23 enable-method = "psci";
24 next-level-cache = <&l2>;
29 compatible = "arm,psci-0.2";
35 compatible = "fixed-clock";
37 clock-frequency = <25000000>;
40 arm_timer_clk: arm_timer_clk {
42 compatible = "fixed-clock";
43 clock-frequency = <50000000>;
48 compatible = "simple-bus";
52 interrupt-parent = <&intc>;
55 l2: l2-cache@500c0000 {
56 compatible = "socionext,uniphier-system-cache";
57 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
59 interrupts = <0 174 4>, <0 175 4>;
61 cache-size = <(256 * 1024)>;
63 cache-line-size = <128>;
67 serial0: serial@54006800 {
68 compatible = "socionext,uniphier-uart";
70 reg = <0x54006800 0x40>;
71 interrupts = <0 33 4>;
72 pinctrl-names = "default";
73 pinctrl-0 = <&pinctrl_uart0>;
74 clocks = <&peri_clk 0>;
75 clock-frequency = <80000000>;
78 serial1: serial@54006900 {
79 compatible = "socionext,uniphier-uart";
81 reg = <0x54006900 0x40>;
82 interrupts = <0 35 4>;
83 pinctrl-names = "default";
84 pinctrl-0 = <&pinctrl_uart1>;
85 clocks = <&peri_clk 1>;
86 clock-frequency = <80000000>;
89 serial2: serial@54006a00 {
90 compatible = "socionext,uniphier-uart";
92 reg = <0x54006a00 0x40>;
93 interrupts = <0 37 4>;
94 pinctrl-names = "default";
95 pinctrl-0 = <&pinctrl_uart2>;
96 clocks = <&peri_clk 2>;
97 clock-frequency = <80000000>;
100 serial3: serial@54006b00 {
101 compatible = "socionext,uniphier-uart";
103 reg = <0x54006b00 0x40>;
104 interrupts = <0 29 4>;
105 pinctrl-names = "default";
106 pinctrl-0 = <&pinctrl_uart3>;
107 clocks = <&peri_clk 3>;
108 clock-frequency = <80000000>;
111 gpio: gpio@55000000 {
112 compatible = "socionext,uniphier-gpio";
113 reg = <0x55000000 0x200>;
114 interrupt-parent = <&aidet>;
115 interrupt-controller;
116 #interrupt-cells = <2>;
119 gpio-ranges = <&pinctrl 0 0 0>,
122 gpio-ranges-group-names = "gpio_range0",
129 compatible = "socionext,uniphier-i2c";
131 reg = <0x58400000 0x40>;
132 #address-cells = <1>;
134 interrupts = <0 41 1>;
135 pinctrl-names = "default";
136 pinctrl-0 = <&pinctrl_i2c0>;
137 clocks = <&peri_clk 4>;
138 clock-frequency = <100000>;
142 compatible = "socionext,uniphier-i2c";
144 reg = <0x58480000 0x40>;
145 #address-cells = <1>;
147 interrupts = <0 42 1>;
148 pinctrl-names = "default";
149 pinctrl-0 = <&pinctrl_i2c1>;
150 clocks = <&peri_clk 5>;
151 clock-frequency = <100000>;
154 /* chip-internal connection for DMD */
156 compatible = "socionext,uniphier-i2c";
157 reg = <0x58500000 0x40>;
158 #address-cells = <1>;
160 interrupts = <0 43 1>;
161 pinctrl-names = "default";
162 pinctrl-0 = <&pinctrl_i2c2>;
163 clocks = <&peri_clk 6>;
164 clock-frequency = <400000>;
168 compatible = "socionext,uniphier-i2c";
170 reg = <0x58580000 0x40>;
171 #address-cells = <1>;
173 interrupts = <0 44 1>;
174 pinctrl-names = "default";
175 pinctrl-0 = <&pinctrl_i2c3>;
176 clocks = <&peri_clk 7>;
177 clock-frequency = <100000>;
180 system_bus: system-bus@58c00000 {
181 compatible = "socionext,uniphier-system-bus";
183 reg = <0x58c00000 0x400>;
184 #address-cells = <2>;
186 pinctrl-names = "default";
187 pinctrl-0 = <&pinctrl_system_bus>;
191 compatible = "socionext,uniphier-smpctrl";
192 reg = <0x59801000 0x400>;
196 compatible = "socionext,uniphier-sld8-mioctrl",
197 "simple-mfd", "syscon";
198 reg = <0x59810000 0x800>;
201 compatible = "socionext,uniphier-sld8-mio-clock";
206 compatible = "socionext,uniphier-sld8-mio-reset";
212 compatible = "socionext,uniphier-sld8-perictrl",
213 "simple-mfd", "syscon";
214 reg = <0x59820000 0x200>;
217 compatible = "socionext,uniphier-sld8-peri-clock";
222 compatible = "socionext,uniphier-sld8-peri-reset";
228 compatible = "socionext,uniphier-sdhc";
230 reg = <0x5a400000 0x200>;
231 interrupts = <0 76 4>;
232 pinctrl-names = "default", "1.8v";
233 pinctrl-0 = <&pinctrl_sd>;
234 pinctrl-1 = <&pinctrl_sd_1v8>;
235 clocks = <&mio_clk 0>;
236 reset-names = "host", "bridge";
237 resets = <&mio_rst 0>, <&mio_rst 3>;
245 emmc: sdhc@5a500000 {
246 compatible = "socionext,uniphier-sdhc";
248 reg = <0x5a500000 0x200>;
249 interrupts = <0 78 4>;
250 pinctrl-names = "default", "1.8v";
251 pinctrl-0 = <&pinctrl_emmc>;
252 pinctrl-1 = <&pinctrl_emmc_1v8>;
253 clocks = <&mio_clk 1>;
254 reset-names = "host", "bridge";
255 resets = <&mio_rst 1>, <&mio_rst 4>;
263 compatible = "socionext,uniphier-ehci", "generic-ehci";
265 reg = <0x5a800100 0x100>;
266 interrupts = <0 80 4>;
267 pinctrl-names = "default";
268 pinctrl-0 = <&pinctrl_usb0>;
269 clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
270 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
275 compatible = "socionext,uniphier-ehci", "generic-ehci";
277 reg = <0x5a810100 0x100>;
278 interrupts = <0 81 4>;
279 pinctrl-names = "default";
280 pinctrl-0 = <&pinctrl_usb1>;
281 clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
282 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
287 compatible = "socionext,uniphier-ehci", "generic-ehci";
289 reg = <0x5a820100 0x100>;
290 interrupts = <0 82 4>;
291 pinctrl-names = "default";
292 pinctrl-0 = <&pinctrl_usb2>;
293 clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>;
294 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
299 compatible = "socionext,uniphier-sld8-soc-glue",
300 "simple-mfd", "syscon";
301 reg = <0x5f800000 0x2000>;
305 compatible = "socionext,uniphier-sld8-pinctrl";
311 compatible = "arm,cortex-a9-global-timer";
312 reg = <0x60000200 0x20>;
313 interrupts = <1 11 0x104>;
314 clocks = <&arm_timer_clk>;
318 compatible = "arm,cortex-a9-twd-timer";
319 reg = <0x60000600 0x20>;
320 interrupts = <1 13 0x104>;
321 clocks = <&arm_timer_clk>;
324 intc: interrupt-controller@60001000 {
325 compatible = "arm,cortex-a9-gic";
326 reg = <0x60001000 0x1000>,
328 #interrupt-cells = <3>;
329 interrupt-controller;
332 aidet: aidet@61830000 {
333 compatible = "socionext,uniphier-sld8-aidet";
334 reg = <0x61830000 0x200>;
335 interrupt-controller;
336 #interrupt-cells = <2>;
340 compatible = "socionext,uniphier-sld8-sysctrl",
341 "simple-mfd", "syscon";
342 reg = <0x61840000 0x10000>;
345 compatible = "socionext,uniphier-sld8-clock";
350 compatible = "socionext,uniphier-sld8-reset";
355 nand: nand@68000000 {
356 compatible = "socionext,uniphier-denali-nand-v5a";
358 reg-names = "nand_data", "denali_reg";
359 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
360 interrupts = <0 65 4>;
361 pinctrl-names = "default";
362 pinctrl-0 = <&pinctrl_nand2cs>;
363 clocks = <&sys_clk 2>;
368 #include "uniphier-pinctrl.dtsi"