git.sur5r.net Git - u-boot/blob - arch/arm/dts/uniphier-sld8.dtsi

   1 /*
   2  * Device Tree Source for UniPhier sLD8 SoC
   3  *
   4  * Copyright (C) 2015-2016 Socionext Inc.
   5  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
   6  *
   7  * This file is dual-licensed: you can use it either under the terms
   8  * of the GPL or the X11 license, at your option. Note that this dual
   9  * licensing only applies to this file, and not this project as a
  10  * whole.
  11  *
  12  *  a) This file is free software; you can redistribute it and/or
  13  *     modify it under the terms of the GNU General Public License as
  14  *     published by the Free Software Foundation; either version 2 of the
  15  *     License, or (at your option) any later version.
  16  *
  17  *     This file is distributed in the hope that it will be useful,
  18  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  *     GNU General Public License for more details.
  21  *
  22  * Or, alternatively,
  23  *
  24  *  b) Permission is hereby granted, free of charge, to any person
  25  *     obtaining a copy of this software and associated documentation
  26  *     files (the "Software"), to deal in the Software without
  27  *     restriction, including without limitation the rights to use,
  28  *     copy, modify, merge, publish, distribute, sublicense, and/or
  29  *     sell copies of the Software, and to permit persons to whom the
  30  *     Software is furnished to do so, subject to the following
  31  *     conditions:
  32  *
  33  *     The above copyright notice and this permission notice shall be
  34  *     included in all copies or substantial portions of the Software.
  35  *
  36  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  37  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  38  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  39  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  40  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  41  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  42  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  43  *     OTHER DEALINGS IN THE SOFTWARE.
  44  */
  45
  46 / {
  47         compatible = "socionext,uniphier-sld8";
  48         #address-cells = <1>;
  49         #size-cells = <1>;
  50
  51         cpus {
  52                 #address-cells = <1>;
  53                 #size-cells = <0>;
  54
  55                 cpu@0 {
  56                         device_type = "cpu";
  57                         compatible = "arm,cortex-a9";
  58                         reg = <0>;
  59                         enable-method = "psci";
  60                         next-level-cache = <&l2>;
  61                 };
  62         };
  63
  64         psci {
  65                 compatible = "arm,psci-0.2";
  66                 method = "smc";
  67         };
  68
  69         clocks {
  70                 refclk: ref {
  71                         compatible = "fixed-clock";
  72                         #clock-cells = <0>;
  73                         clock-frequency = <25000000>;
  74                 };
  75
  76                 arm_timer_clk: arm_timer_clk {
  77                         #clock-cells = <0>;
  78                         compatible = "fixed-clock";
  79                         clock-frequency = <50000000>;
  80                 };
  81         };
  82
  83         soc {
  84                 compatible = "simple-bus";
  85                 #address-cells = <1>;
  86                 #size-cells = <1>;
  87                 ranges;
  88                 interrupt-parent = <&intc>;
  89                 u-boot,dm-pre-reloc;
  90
  91                 l2: l2-cache@500c0000 {
  92                         compatible = "socionext,uniphier-system-cache";
  93                         reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
  94                               <0x506c0000 0x400>;
  95                         interrupts = <0 174 4>, <0 175 4>;
  96                         cache-unified;
  97                         cache-size = <(256 * 1024)>;
  98                         cache-sets = <256>;
  99                         cache-line-size = <128>;
 100                         cache-level = <2>;
 101                 };
 102
 103                 serial0: serial@54006800 {
 104                         compatible = "socionext,uniphier-uart";
 105                         status = "disabled";
 106                         reg = <0x54006800 0x40>;
 107                         interrupts = <0 33 4>;
 108                         pinctrl-names = "default";
 109                         pinctrl-0 = <&pinctrl_uart0>;
 110                         clocks = <&peri_clk 0>;
 111                         clock-frequency = <80000000>;
 112                 };
 113
 114                 serial1: serial@54006900 {
 115                         compatible = "socionext,uniphier-uart";
 116                         status = "disabled";
 117                         reg = <0x54006900 0x40>;
 118                         interrupts = <0 35 4>;
 119                         pinctrl-names = "default";
 120                         pinctrl-0 = <&pinctrl_uart1>;
 121                         clocks = <&peri_clk 1>;
 122                         clock-frequency = <80000000>;
 123                 };
 124
 125                 serial2: serial@54006a00 {
 126                         compatible = "socionext,uniphier-uart";
 127                         status = "disabled";
 128                         reg = <0x54006a00 0x40>;
 129                         interrupts = <0 37 4>;
 130                         pinctrl-names = "default";
 131                         pinctrl-0 = <&pinctrl_uart2>;
 132                         clocks = <&peri_clk 2>;
 133                         clock-frequency = <80000000>;
 134                 };
 135
 136                 serial3: serial@54006b00 {
 137                         compatible = "socionext,uniphier-uart";
 138                         status = "disabled";
 139                         reg = <0x54006b00 0x40>;
 140                         interrupts = <0 29 4>;
 141                         pinctrl-names = "default";
 142                         pinctrl-0 = <&pinctrl_uart3>;
 143                         clocks = <&peri_clk 3>;
 144                         clock-frequency = <80000000>;
 145                 };
 146
 147                 port0x: gpio@55000008 {
 148                         compatible = "socionext,uniphier-gpio";
 149                         reg = <0x55000008 0x8>;
 150                         gpio-controller;
 151                         #gpio-cells = <2>;
 152                 };
 153
 154                 port1x: gpio@55000010 {
 155                         compatible = "socionext,uniphier-gpio";
 156                         reg = <0x55000010 0x8>;
 157                         gpio-controller;
 158                         #gpio-cells = <2>;
 159                 };
 160
 161                 port2x: gpio@55000018 {
 162                         compatible = "socionext,uniphier-gpio";
 163                         reg = <0x55000018 0x8>;
 164                         gpio-controller;
 165                         #gpio-cells = <2>;
 166                 };
 167
 168                 port3x: gpio@55000020 {
 169                         compatible = "socionext,uniphier-gpio";
 170                         reg = <0x55000020 0x8>;
 171                         gpio-controller;
 172                         #gpio-cells = <2>;
 173                 };
 174
 175                 port4: gpio@55000028 {
 176                         compatible = "socionext,uniphier-gpio";
 177                         reg = <0x55000028 0x8>;
 178                         gpio-controller;
 179                         #gpio-cells = <2>;
 180                 };
 181
 182                 port5x: gpio@55000030 {
 183                         compatible = "socionext,uniphier-gpio";
 184                         reg = <0x55000030 0x8>;
 185                         gpio-controller;
 186                         #gpio-cells = <2>;
 187                 };
 188
 189                 port6x: gpio@55000038 {
 190                         compatible = "socionext,uniphier-gpio";
 191                         reg = <0x55000038 0x8>;
 192                         gpio-controller;
 193                         #gpio-cells = <2>;
 194                 };
 195
 196                 port7x: gpio@55000040 {
 197                         compatible = "socionext,uniphier-gpio";
 198                         reg = <0x55000040 0x8>;
 199                         gpio-controller;
 200                         #gpio-cells = <2>;
 201                 };
 202
 203                 port8x: gpio@55000048 {
 204                         compatible = "socionext,uniphier-gpio";
 205                         reg = <0x55000048 0x8>;
 206                         gpio-controller;
 207                         #gpio-cells = <2>;
 208                 };
 209
 210                 port9x: gpio@55000050 {
 211                         compatible = "socionext,uniphier-gpio";
 212                         reg = <0x55000050 0x8>;
 213                         gpio-controller;
 214                         #gpio-cells = <2>;
 215                 };
 216
 217                 port10x: gpio@55000058 {
 218                         compatible = "socionext,uniphier-gpio";
 219                         reg = <0x55000058 0x8>;
 220                         gpio-controller;
 221                         #gpio-cells = <2>;
 222                 };
 223
 224                 port11x: gpio@55000060 {
 225                         compatible = "socionext,uniphier-gpio";
 226                         reg = <0x55000060 0x8>;
 227                         gpio-controller;
 228                         #gpio-cells = <2>;
 229                 };
 230
 231                 port12x: gpio@55000068 {
 232                         compatible = "socionext,uniphier-gpio";
 233                         reg = <0x55000068 0x8>;
 234                         gpio-controller;
 235                         #gpio-cells = <2>;
 236                 };
 237
 238                 port13x: gpio@55000070 {
 239                         compatible = "socionext,uniphier-gpio";
 240                         reg = <0x55000070 0x8>;
 241                         gpio-controller;
 242                         #gpio-cells = <2>;
 243                 };
 244
 245                 port14x: gpio@55000078 {
 246                         compatible = "socionext,uniphier-gpio";
 247                         reg = <0x55000078 0x8>;
 248                         gpio-controller;
 249                         #gpio-cells = <2>;
 250                 };
 251
 252                 port16x: gpio@55000088 {
 253                         compatible = "socionext,uniphier-gpio";
 254                         reg = <0x55000088 0x8>;
 255                         gpio-controller;
 256                         #gpio-cells = <2>;
 257                 };
 258
 259                 i2c0: i2c@58400000 {
 260                         compatible = "socionext,uniphier-i2c";
 261                         status = "disabled";
 262                         reg = <0x58400000 0x40>;
 263                         #address-cells = <1>;
 264                         #size-cells = <0>;
 265                         interrupts = <0 41 1>;
 266                         pinctrl-names = "default";
 267                         pinctrl-0 = <&pinctrl_i2c0>;
 268                         clocks = <&peri_clk 4>;
 269                         clock-frequency = <100000>;
 270                 };
 271
 272                 i2c1: i2c@58480000 {
 273                         compatible = "socionext,uniphier-i2c";
 274                         status = "disabled";
 275                         reg = <0x58480000 0x40>;
 276                         #address-cells = <1>;
 277                         #size-cells = <0>;
 278                         interrupts = <0 42 1>;
 279                         pinctrl-names = "default";
 280                         pinctrl-0 = <&pinctrl_i2c1>;
 281                         clocks = <&peri_clk 5>;
 282                         clock-frequency = <100000>;
 283                 };
 284
 285                 /* chip-internal connection for DMD */
 286                 i2c2: i2c@58500000 {
 287                         compatible = "socionext,uniphier-i2c";
 288                         reg = <0x58500000 0x40>;
 289                         #address-cells = <1>;
 290                         #size-cells = <0>;
 291                         interrupts = <0 43 1>;
 292                         pinctrl-names = "default";
 293                         pinctrl-0 = <&pinctrl_i2c2>;
 294                         clocks = <&peri_clk 6>;
 295                         clock-frequency = <400000>;
 296                 };
 297
 298                 i2c3: i2c@58580000 {
 299                         compatible = "socionext,uniphier-i2c";
 300                         status = "disabled";
 301                         reg = <0x58580000 0x40>;
 302                         #address-cells = <1>;
 303                         #size-cells = <0>;
 304                         interrupts = <0 44 1>;
 305                         pinctrl-names = "default";
 306                         pinctrl-0 = <&pinctrl_i2c3>;
 307                         clocks = <&peri_clk 7>;
 308                         clock-frequency = <100000>;
 309                 };
 310
 311                 system_bus: system-bus@58c00000 {
 312                         compatible = "socionext,uniphier-system-bus";
 313                         status = "disabled";
 314                         reg = <0x58c00000 0x400>;
 315                         #address-cells = <2>;
 316                         #size-cells = <1>;
 317                         pinctrl-names = "default";
 318                         pinctrl-0 = <&pinctrl_system_bus>;
 319                 };
 320
 321                 smpctrl@59801000 {
 322                         compatible = "socionext,uniphier-smpctrl";
 323                         reg = <0x59801000 0x400>;
 324                 };
 325
 326                 mioctrl@59810000 {
 327                         compatible = "socionext,uniphier-sld8-mioctrl",
 328                                      "simple-mfd", "syscon";
 329                         reg = <0x59810000 0x800>;
 330
 331                         mio_clk: clock {
 332                                 compatible = "socionext,uniphier-sld8-mio-clock";
 333                                 #clock-cells = <1>;
 334                         };
 335
 336                         mio_rst: reset {
 337                                 compatible = "socionext,uniphier-sld8-mio-reset";
 338                                 #reset-cells = <1>;
 339                         };
 340                 };
 341
 342                 perictrl@59820000 {
 343                         compatible = "socionext,uniphier-sld8-perictrl",
 344                                      "simple-mfd", "syscon";
 345                         reg = <0x59820000 0x200>;
 346
 347                         peri_clk: clock {
 348                                 compatible = "socionext,uniphier-sld8-peri-clock";
 349                                 #clock-cells = <1>;
 350                         };
 351
 352                         peri_rst: reset {
 353                                 compatible = "socionext,uniphier-sld8-peri-reset";
 354                                 #reset-cells = <1>;
 355                         };
 356                 };
 357
 358                 sd: sdhc@5a400000 {
 359                         compatible = "socionext,uniphier-sdhc";
 360                         status = "disabled";
 361                         reg = <0x5a400000 0x200>;
 362                         interrupts = <0 76 4>;
 363                         pinctrl-names = "default", "1.8v";
 364                         pinctrl-0 = <&pinctrl_sd>;
 365                         pinctrl-1 = <&pinctrl_sd_1v8>;
 366                         clocks = <&mio_clk 0>;
 367                         reset-names = "host", "bridge";
 368                         resets = <&mio_rst 0>, <&mio_rst 3>;
 369                         bus-width = <4>;
 370                         cap-sd-highspeed;
 371                         sd-uhs-sdr12;
 372                         sd-uhs-sdr25;
 373                         sd-uhs-sdr50;
 374                 };
 375
 376                 emmc: sdhc@5a500000 {
 377                         compatible = "socionext,uniphier-sdhc";
 378                         status = "disabled";
 379                         reg = <0x5a500000 0x200>;
 380                         interrupts = <0 78 4>;
 381                         pinctrl-names = "default", "1.8v";
 382                         pinctrl-0 = <&pinctrl_emmc>;
 383                         pinctrl-1 = <&pinctrl_emmc_1v8>;
 384                         clocks = <&mio_clk 1>;
 385                         reset-names = "host", "bridge";
 386                         resets = <&mio_rst 1>, <&mio_rst 4>;
 387                         bus-width = <8>;
 388                         non-removable;
 389                         cap-mmc-highspeed;
 390                         cap-mmc-hw-reset;
 391                 };
 392
 393                 usb0: usb@5a800100 {
 394                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 395                         status = "disabled";
 396                         reg = <0x5a800100 0x100>;
 397                         interrupts = <0 80 4>;
 398                         pinctrl-names = "default";
 399                         pinctrl-0 = <&pinctrl_usb0>;
 400                         clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
 401                         resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
 402                                  <&mio_rst 12>;
 403                 };
 404
 405                 usb1: usb@5a810100 {
 406                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 407                         status = "disabled";
 408                         reg = <0x5a810100 0x100>;
 409                         interrupts = <0 81 4>;
 410                         pinctrl-names = "default";
 411                         pinctrl-0 = <&pinctrl_usb1>;
 412                         clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
 413                         resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
 414                                  <&mio_rst 13>;
 415                 };
 416
 417                 usb2: usb@5a820100 {
 418                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 419                         status = "disabled";
 420                         reg = <0x5a820100 0x100>;
 421                         interrupts = <0 82 4>;
 422                         pinctrl-names = "default";
 423                         pinctrl-0 = <&pinctrl_usb2>;
 424                         clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>;
 425                         resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
 426                                  <&mio_rst 14>;
 427                 };
 428
 429                 soc-glue@5f800000 {
 430                         compatible = "socionext,uniphier-sld8-soc-glue",
 431                                      "simple-mfd", "syscon";
 432                         reg = <0x5f800000 0x2000>;
 433                         u-boot,dm-pre-reloc;
 434
 435                         pinctrl: pinctrl {
 436                                 compatible = "socionext,uniphier-sld8-pinctrl";
 437                                 u-boot,dm-pre-reloc;
 438                         };
 439                 };
 440
 441                 timer@60000200 {
 442                         compatible = "arm,cortex-a9-global-timer";
 443                         reg = <0x60000200 0x20>;
 444                         interrupts = <1 11 0x104>;
 445                         clocks = <&arm_timer_clk>;
 446                 };
 447
 448                 timer@60000600 {
 449                         compatible = "arm,cortex-a9-twd-timer";
 450                         reg = <0x60000600 0x20>;
 451                         interrupts = <1 13 0x104>;
 452                         clocks = <&arm_timer_clk>;
 453                 };
 454
 455                 intc: interrupt-controller@60001000 {
 456                         compatible = "arm,cortex-a9-gic";
 457                         reg = <0x60001000 0x1000>,
 458                               <0x60000100 0x100>;
 459                         #interrupt-cells = <3>;
 460                         interrupt-controller;
 461                 };
 462
 463                 aidet@61830000 {
 464                         compatible = "simple-mfd", "syscon";
 465                         reg = <0x61830000 0x200>;
 466                 };
 467
 468                 sysctrl@61840000 {
 469                         compatible = "socionext,uniphier-sld8-sysctrl",
 470                                      "simple-mfd", "syscon";
 471                         reg = <0x61840000 0x10000>;
 472
 473                         sys_clk: clock {
 474                                 compatible = "socionext,uniphier-sld8-clock";
 475                                 #clock-cells = <1>;
 476                         };
 477
 478                         sys_rst: reset {
 479                                 compatible = "socionext,uniphier-sld8-reset";
 480                                 #reset-cells = <1>;
 481                         };
 482                 };
 483
 484                 nand: nand@68000000 {
 485                         compatible = "socionext,uniphier-denali-nand-v5a";
 486                         status = "disabled";
 487                         reg-names = "nand_data", "denali_reg";
 488                         reg = <0x68000000 0x20>, <0x68100000 0x1000>;
 489                         interrupts = <0 65 4>;
 490                         pinctrl-names = "default";
 491                         pinctrl-0 = <&pinctrl_nand>;
 492                         clocks = <&sys_clk 2>;
 493                         nand-ecc-strength = <8>;
 494                 };
 495         };
 496 };
 497
 498 /include/ "uniphier-pinctrl.dtsi"