git.sur5r.net Git - u-boot/blob - arch/arm/dts/vf.dtsi

   1 /*
   2  * Copyright 2013 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+ or X11
   5  */
   6 /include/ "skeleton.dtsi"
   7
   8 / {
   9         aliases {
  10                 gpio0 = &gpio0;
  11                 gpio1 = &gpio1;
  12                 gpio2 = &gpio2;
  13                 gpio3 = &gpio3;
  14                 gpio4 = &gpio4;
  15                 serial0 = &uart0;
  16                 serial1 = &uart1;
  17                 serial2 = &uart2;
  18                 serial3 = &uart3;
  19                 serial4 = &uart4;
  20                 serial5 = &uart5;
  21                 spi0 = &dspi0;
  22                 spi1 = &dspi1;
  23         };
  24
  25         soc {
  26                 #address-cells = <1>;
  27                 #size-cells = <1>;
  28                 compatible = "simple-bus";
  29                 ranges;
  30
  31                 aips0: aips-bus@40000000 {
  32                         compatible = "fsl,aips-bus", "simple-bus";
  33                         #address-cells = <1>;
  34                         #size-cells = <1>;
  35                         ranges;
  36
  37                         uart0: serial@40027000 {
  38                                 compatible = "fsl,vf610-lpuart";
  39                                 reg = <0x40027000 0x1000>;
  40                                 status = "disabled";
  41                         };
  42
  43                         uart1: serial@40028000 {
  44                                 compatible = "fsl,vf610-lpuart";
  45                                 reg = <0x40028000 0x1000>;
  46                                 status = "disabled";
  47                         };
  48
  49                         uart2: serial@40029000 {
  50                                 compatible = "fsl,vf610-lpuart";
  51                                 reg = <0x40029000 0x1000>;
  52                                 status = "disabled";
  53                         };
  54
  55                         uart3: serial@4002a000 {
  56                                 compatible = "fsl,vf610-lpuart";
  57                                 reg = <0x4002a000 0x1000>;
  58                                 status = "disabled";
  59                         };
  60
  61                         dspi0: dspi0@4002c000 {
  62                                 #address-cells = <1>;
  63                                 #size-cells = <0>;
  64                                 compatible = "fsl,vf610-dspi";
  65                                 reg = <0x4002c000 0x1000>;
  66                                 num-cs = <5>;
  67                                 status = "disabled";
  68                         };
  69
  70                         dspi1: dspi1@4002d000 {
  71                                 #address-cells = <1>;
  72                                 #size-cells = <0>;
  73                                 compatible = "fsl,vf610-dspi";
  74                                 reg = <0x4002d000 0x1000>;
  75                                 num-cs = <5>;
  76                                 status = "disabled";
  77                         };
  78
  79                         qspi0: quadspi@40044000 {
  80                                 #address-cells = <1>;
  81                                 #size-cells = <0>;
  82                                 compatible = "fsl,vf610-qspi";
  83                                 reg = <0x40044000 0x1000>;
  84                                 status = "disabled";
  85                         };
  86
  87                         gpio0: gpio@40049000 {
  88                                 compatible = "fsl,vf610-gpio";
  89                                 reg = <0x400ff000 0x40>;
  90                                 #gpio-cells = <2>;
  91                         };
  92
  93                         gpio1: gpio@4004a000 {
  94                                 compatible = "fsl,vf610-gpio";
  95                                 reg = <0x400ff040 0x40>;
  96                                 #gpio-cells = <2>;
  97                         };
  98
  99                         gpio2: gpio@4004b000 {
 100                                 compatible = "fsl,vf610-gpio";
 101                                 reg = <0x400ff080 0x40>;
 102                                 #gpio-cells = <2>;
 103                         };
 104
 105                         gpio3: gpio@4004c000 {
 106                                 compatible = "fsl,vf610-gpio";
 107                                 reg = <0x400ff0c0 0x40>;
 108                                 #gpio-cells = <2>;
 109                         };
 110
 111                         gpio4: gpio@4004d000 {
 112                                 compatible = "fsl,vf610-gpio";
 113                                 reg = <0x400ff100 0x40>;
 114                                 #gpio-cells = <2>;
 115                         };
 116                 };
 117
 118                 aips1: aips-bus@40080000 {
 119                         compatible = "fsl,aips-bus", "simple-bus";
 120                         #address-cells = <1>;
 121                         #size-cells = <1>;
 122                         ranges;
 123
 124                         uart4: serial@400a9000 {
 125                                 compatible = "fsl,vf610-lpuart";
 126                                 reg = <0x400a9000 0x1000>;
 127                                 status = "disabled";
 128                         };
 129
 130                         uart5: serial@400aa000 {
 131                                 compatible = "fsl,vf610-lpuart";
 132                                 reg = <0x400aa000 0x1000>;
 133                                 status = "disabled";
 134                         };
 135
 136                 };
 137         };
 138 };