2 * Xilinx Zynq 7000 DTSI
3 * Describes the hardware common to all Zynq 7000-based boards.
5 * Copyright (C) 2011 - 2015 Xilinx
7 * SPDX-License-Identifier: GPL-2.0+
9 /include/ "skeleton.dtsi"
12 compatible = "xlnx,zynq-7000";
19 compatible = "arm,cortex-a9";
23 clock-latency = <1000>;
24 cpu0-supply = <®ulator_vccpint>;
33 compatible = "arm,cortex-a9";
41 compatible = "arm,cortex-a9-pmu";
42 interrupts = <0 5 4>, <0 6 4>;
43 interrupt-parent = <&intc>;
44 reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >;
47 regulator_vccpint: fixedregulator@0 {
48 compatible = "regulator-fixed";
49 regulator-name = "VCCPINT";
50 regulator-min-microvolt = <1000000>;
51 regulator-max-microvolt = <1000000>;
58 compatible = "simple-bus";
61 interrupt-parent = <&intc>;
65 compatible = "xlnx,zynq-xadc-1.00.a";
66 reg = <0xf8007100 0x20>;
68 interrupt-parent = <&intc>;
73 compatible = "xlnx,zynq-can-1.0";
75 clocks = <&clkc 19>, <&clkc 36>;
76 clock-names = "can_clk", "pclk";
77 reg = <0xe0008000 0x1000>;
78 interrupts = <0 28 4>;
79 interrupt-parent = <&intc>;
80 tx-fifo-depth = <0x40>;
81 rx-fifo-depth = <0x40>;
85 compatible = "xlnx,zynq-can-1.0";
87 clocks = <&clkc 20>, <&clkc 37>;
88 clock-names = "can_clk", "pclk";
89 reg = <0xe0009000 0x1000>;
90 interrupts = <0 51 4>;
91 interrupt-parent = <&intc>;
92 tx-fifo-depth = <0x40>;
93 rx-fifo-depth = <0x40>;
96 gpio0: gpio@e000a000 {
97 compatible = "xlnx,zynq-gpio-1.0";
101 interrupt-parent = <&intc>;
102 interrupts = <0 20 4>;
103 reg = <0xe000a000 0x1000>;
107 compatible = "cdns,i2c-r1p10";
110 interrupt-parent = <&intc>;
111 interrupts = <0 25 4>;
112 reg = <0xe0004000 0x1000>;
113 #address-cells = <1>;
118 compatible = "cdns,i2c-r1p10";
121 interrupt-parent = <&intc>;
122 interrupts = <0 48 4>;
123 reg = <0xe0005000 0x1000>;
124 #address-cells = <1>;
128 intc: interrupt-controller@f8f01000 {
129 compatible = "arm,cortex-a9-gic";
130 #interrupt-cells = <3>;
131 interrupt-controller;
132 reg = <0xF8F01000 0x1000>,
136 L2: cache-controller@f8f02000 {
137 compatible = "arm,pl310-cache";
138 reg = <0xF8F02000 0x1000>;
139 interrupts = <0 2 4>;
140 arm,data-latency = <3 2 2>;
141 arm,tag-latency = <2 2 2>;
146 mc: memory-controller@f8006000 {
147 compatible = "xlnx,zynq-ddrc-a05";
148 reg = <0xf8006000 0x1000>;
151 uart0: serial@e0000000 {
152 compatible = "xlnx,xuartps", "cdns,uart-r1p8";
154 clocks = <&clkc 23>, <&clkc 40>;
155 clock-names = "uart_clk", "pclk";
156 reg = <0xE0000000 0x1000>;
157 interrupts = <0 27 4>;
160 uart1: serial@e0001000 {
161 compatible = "xlnx,xuartps", "cdns,uart-r1p8";
163 clocks = <&clkc 24>, <&clkc 41>;
164 clock-names = "uart_clk", "pclk";
165 reg = <0xE0001000 0x1000>;
166 interrupts = <0 50 4>;
170 compatible = "xlnx,zynq-spi-r1p6";
171 reg = <0xe0006000 0x1000>;
173 interrupt-parent = <&intc>;
174 interrupts = <0 26 4>;
175 clocks = <&clkc 25>, <&clkc 34>;
176 clock-names = "ref_clk", "pclk";
177 spi-max-frequency = <166666700>;
178 #address-cells = <1>;
183 compatible = "xlnx,zynq-spi-r1p6";
184 reg = <0xe0007000 0x1000>;
186 interrupt-parent = <&intc>;
187 interrupts = <0 49 4>;
188 clocks = <&clkc 26>, <&clkc 35>;
189 clock-names = "ref_clk", "pclk";
190 spi-max-frequency = <166666700>;
191 #address-cells = <1>;
196 clock-names = "ref_clk", "pclk";
197 clocks = <&clkc 10>, <&clkc 43>;
198 compatible = "xlnx,zynq-qspi-1.0";
200 interrupt-parent = <&intc>;
201 interrupts = <0 19 4>;
202 reg = <0xe000d000 0x1000>;
203 #address-cells = <1>;
207 gem0: ethernet@e000b000 {
208 compatible = "cdns,zynq-gem", "cdns,gem";
209 reg = <0xe000b000 0x1000>;
211 interrupts = <0 22 4>;
212 clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
213 clock-names = "pclk", "hclk", "tx_clk";
214 #address-cells = <1>;
218 gem1: ethernet@e000c000 {
219 compatible = "cdns,zynq-gem", "cdns,gem";
220 reg = <0xe000c000 0x1000>;
222 interrupts = <0 45 4>;
223 clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;
224 clock-names = "pclk", "hclk", "tx_clk";
225 #address-cells = <1>;
229 sdhci0: sdhci@e0100000 {
230 compatible = "arasan,sdhci-8.9a";
232 clock-names = "clk_xin", "clk_ahb";
233 clocks = <&clkc 21>, <&clkc 32>;
234 interrupt-parent = <&intc>;
235 interrupts = <0 24 4>;
236 reg = <0xe0100000 0x1000>;
239 sdhci1: sdhci@e0101000 {
240 compatible = "arasan,sdhci-8.9a";
242 clock-names = "clk_xin", "clk_ahb";
243 clocks = <&clkc 22>, <&clkc 33>;
244 interrupt-parent = <&intc>;
245 interrupts = <0 47 4>;
246 reg = <0xe0101000 0x1000>;
249 slcr: slcr@f8000000 {
250 #address-cells = <1>;
252 compatible = "xlnx,zynq-slcr", "syscon", "simple-bus";
253 reg = <0xF8000000 0x1000>;
257 compatible = "xlnx,ps7-clkc";
259 clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
260 "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
261 "dci", "lqspi", "smc", "pcap", "gem0", "gem1",
262 "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
263 "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
264 "dma", "usb0_aper", "usb1_aper", "gem0_aper",
265 "gem1_aper", "sdio0_aper", "sdio1_aper",
266 "spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
267 "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
268 "gpio_aper", "lqspi_aper", "smc_aper", "swdt",
269 "dbg_trc", "dbg_apb";
273 pinctrl0: pinctrl@700 {
274 compatible = "xlnx,pinctrl-zynq";
280 dmac_s: dmac@f8003000 {
281 compatible = "arm,pl330", "arm,primecell";
282 reg = <0xf8003000 0x1000>;
283 interrupt-parent = <&intc>;
284 interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3",
285 "dma4", "dma5", "dma6", "dma7";
286 interrupts = <0 13 4>,
295 clock-names = "apb_pclk";
298 devcfg: devcfg@f8007000 {
299 compatible = "xlnx,zynq-devcfg-1.0";
300 reg = <0xf8007000 0x100>;
303 global_timer: timer@f8f00200 {
304 compatible = "arm,cortex-a9-global-timer";
305 reg = <0xf8f00200 0x20>;
306 interrupts = <1 11 0x301>;
307 interrupt-parent = <&intc>;
311 ttc0: timer@f8001000 {
312 interrupt-parent = <&intc>;
313 interrupts = <0 10 4>, <0 11 4>, <0 12 4>;
314 compatible = "cdns,ttc";
316 reg = <0xF8001000 0x1000>;
319 ttc1: timer@f8002000 {
320 interrupt-parent = <&intc>;
321 interrupts = <0 37 4>, <0 38 4>, <0 39 4>;
322 compatible = "cdns,ttc";
324 reg = <0xF8002000 0x1000>;
327 scutimer: timer@f8f00600 {
328 interrupt-parent = <&intc>;
329 interrupts = < 1 13 0x301 >;
330 compatible = "arm,cortex-a9-twd-timer";
331 reg = < 0xf8f00600 0x20 >;
336 compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
339 interrupt-parent = <&intc>;
340 interrupts = <0 21 4>;
341 reg = <0xe0002000 0x1000>;
346 compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
349 interrupt-parent = <&intc>;
350 interrupts = <0 44 4>;
351 reg = <0xe0003000 0x1000>;
355 watchdog0: watchdog@f8005000 {
357 compatible = "cdns,wdt-r1p2";
358 interrupt-parent = <&intc>;
359 interrupts = <0 9 1>;
360 reg = <0xf8005000 0x1000>;