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[u-boot] / arch / arm / dts / zynq-7000.dtsi
1 /*
2  * Xilinx Zynq 7000 DTSI
3  * Describes the hardware common to all Zynq 7000-based boards.
4  *
5  *  Copyright (C) 2011 - 2015 Xilinx
6  *
7  * SPDX-License-Identifier:     GPL-2.0+
8  */
9 /include/ "skeleton.dtsi"
10
11 / {
12         compatible = "xlnx,zynq-7000";
13
14         cpus {
15                 #address-cells = <1>;
16                 #size-cells = <0>;
17
18                 cpu@0 {
19                         compatible = "arm,cortex-a9";
20                         device_type = "cpu";
21                         reg = <0>;
22                         clocks = <&clkc 3>;
23                         clock-latency = <1000>;
24                         cpu0-supply = <&regulator_vccpint>;
25                         operating-points = <
26                                 /* kHz    uV */
27                                 666667  1000000
28                                 333334  1000000
29                         >;
30                 };
31
32                 cpu@1 {
33                         compatible = "arm,cortex-a9";
34                         device_type = "cpu";
35                         reg = <1>;
36                         clocks = <&clkc 3>;
37                 };
38         };
39
40         pmu {
41                 compatible = "arm,cortex-a9-pmu";
42                 interrupts = <0 5 4>, <0 6 4>;
43                 interrupt-parent = <&intc>;
44                 reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >;
45         };
46
47         regulator_vccpint: fixedregulator@0 {
48                 compatible = "regulator-fixed";
49                 regulator-name = "VCCPINT";
50                 regulator-min-microvolt = <1000000>;
51                 regulator-max-microvolt = <1000000>;
52                 regulator-boot-on;
53                 regulator-always-on;
54         };
55
56         amba: amba {
57                 u-boot,dm-pre-reloc;
58                 compatible = "simple-bus";
59                 #address-cells = <1>;
60                 #size-cells = <1>;
61                 interrupt-parent = <&intc>;
62                 ranges;
63
64                 adc: adc@f8007100 {
65                         compatible = "xlnx,zynq-xadc-1.00.a";
66                         reg = <0xf8007100 0x20>;
67                         interrupts = <0 7 4>;
68                         interrupt-parent = <&intc>;
69                         clocks = <&clkc 12>;
70                 };
71
72                 can0: can@e0008000 {
73                         compatible = "xlnx,zynq-can-1.0";
74                         status = "disabled";
75                         clocks = <&clkc 19>, <&clkc 36>;
76                         clock-names = "can_clk", "pclk";
77                         reg = <0xe0008000 0x1000>;
78                         interrupts = <0 28 4>;
79                         interrupt-parent = <&intc>;
80                         tx-fifo-depth = <0x40>;
81                         rx-fifo-depth = <0x40>;
82                 };
83
84                 can1: can@e0009000 {
85                         compatible = "xlnx,zynq-can-1.0";
86                         status = "disabled";
87                         clocks = <&clkc 20>, <&clkc 37>;
88                         clock-names = "can_clk", "pclk";
89                         reg = <0xe0009000 0x1000>;
90                         interrupts = <0 51 4>;
91                         interrupt-parent = <&intc>;
92                         tx-fifo-depth = <0x40>;
93                         rx-fifo-depth = <0x40>;
94                 };
95
96                 gpio0: gpio@e000a000 {
97                         compatible = "xlnx,zynq-gpio-1.0";
98                         #gpio-cells = <2>;
99                         #interrupt-cells = <2>;
100                         clocks = <&clkc 42>;
101                         gpio-controller;
102                         interrupt-controller;
103                         interrupt-parent = <&intc>;
104                         interrupts = <0 20 4>;
105                         reg = <0xe000a000 0x1000>;
106                 };
107
108                 i2c0: i2c@e0004000 {
109                         compatible = "cdns,i2c-r1p10";
110                         status = "disabled";
111                         clocks = <&clkc 38>;
112                         interrupt-parent = <&intc>;
113                         interrupts = <0 25 4>;
114                         reg = <0xe0004000 0x1000>;
115                         #address-cells = <1>;
116                         #size-cells = <0>;
117                 };
118
119                 i2c1: i2c@e0005000 {
120                         compatible = "cdns,i2c-r1p10";
121                         status = "disabled";
122                         clocks = <&clkc 39>;
123                         interrupt-parent = <&intc>;
124                         interrupts = <0 48 4>;
125                         reg = <0xe0005000 0x1000>;
126                         #address-cells = <1>;
127                         #size-cells = <0>;
128                 };
129
130                 intc: interrupt-controller@f8f01000 {
131                         compatible = "arm,cortex-a9-gic";
132                         #interrupt-cells = <3>;
133                         interrupt-controller;
134                         reg = <0xF8F01000 0x1000>,
135                               <0xF8F00100 0x100>;
136                 };
137
138                 L2: cache-controller@f8f02000 {
139                         compatible = "arm,pl310-cache";
140                         reg = <0xF8F02000 0x1000>;
141                         interrupts = <0 2 4>;
142                         arm,data-latency = <3 2 2>;
143                         arm,tag-latency = <2 2 2>;
144                         cache-unified;
145                         cache-level = <2>;
146                 };
147
148                 mc: memory-controller@f8006000 {
149                         compatible = "xlnx,zynq-ddrc-a05";
150                         reg = <0xf8006000 0x1000>;
151                 };
152
153                 uart0: serial@e0000000 {
154                         compatible = "xlnx,xuartps", "cdns,uart-r1p8";
155                         status = "disabled";
156                         clocks = <&clkc 23>, <&clkc 40>;
157                         clock-names = "uart_clk", "pclk";
158                         reg = <0xE0000000 0x1000>;
159                         interrupts = <0 27 4>;
160                 };
161
162                 uart1: serial@e0001000 {
163                         compatible = "xlnx,xuartps", "cdns,uart-r1p8";
164                         status = "disabled";
165                         clocks = <&clkc 24>, <&clkc 41>;
166                         clock-names = "uart_clk", "pclk";
167                         reg = <0xE0001000 0x1000>;
168                         interrupts = <0 50 4>;
169                 };
170
171                 spi0: spi@e0006000 {
172                         compatible = "xlnx,zynq-spi-r1p6";
173                         reg = <0xe0006000 0x1000>;
174                         status = "disabled";
175                         interrupt-parent = <&intc>;
176                         interrupts = <0 26 4>;
177                         clocks = <&clkc 25>, <&clkc 34>;
178                         clock-names = "ref_clk", "pclk";
179                         spi-max-frequency = <166666700>;
180                         #address-cells = <1>;
181                         #size-cells = <0>;
182                 };
183
184                 spi1: spi@e0007000 {
185                         compatible = "xlnx,zynq-spi-r1p6";
186                         reg = <0xe0007000 0x1000>;
187                         status = "disabled";
188                         interrupt-parent = <&intc>;
189                         interrupts = <0 49 4>;
190                         clocks = <&clkc 26>, <&clkc 35>;
191                         clock-names = "ref_clk", "pclk";
192                         spi-max-frequency = <166666700>;
193                         #address-cells = <1>;
194                         #size-cells = <0>;
195                 };
196
197                 qspi: spi@e000d000 {
198                         clock-names = "ref_clk", "pclk";
199                         clocks = <&clkc 10>, <&clkc 43>;
200                         compatible = "xlnx,zynq-qspi-1.0";
201                         status = "disabled";
202                         interrupt-parent = <&intc>;
203                         interrupts = <0 19 4>;
204                         reg = <0xe000d000 0x1000>;
205                         #address-cells = <1>;
206                         #size-cells = <0>;
207                 };
208
209                 gem0: ethernet@e000b000 {
210                         compatible = "cdns,zynq-gem", "cdns,gem";
211                         reg = <0xe000b000 0x1000>;
212                         status = "disabled";
213                         interrupts = <0 22 4>;
214                         clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
215                         clock-names = "pclk", "hclk", "tx_clk";
216                         #address-cells = <1>;
217                         #size-cells = <0>;
218                 };
219
220                 gem1: ethernet@e000c000 {
221                         compatible = "cdns,zynq-gem", "cdns,gem";
222                         reg = <0xe000c000 0x1000>;
223                         status = "disabled";
224                         interrupts = <0 45 4>;
225                         clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;
226                         clock-names = "pclk", "hclk", "tx_clk";
227                         #address-cells = <1>;
228                         #size-cells = <0>;
229                 };
230
231                 sdhci0: sdhci@e0100000 {
232                         compatible = "arasan,sdhci-8.9a";
233                         status = "disabled";
234                         clock-names = "clk_xin", "clk_ahb";
235                         clocks = <&clkc 21>, <&clkc 32>;
236                         interrupt-parent = <&intc>;
237                         interrupts = <0 24 4>;
238                         reg = <0xe0100000 0x1000>;
239                 };
240
241                 sdhci1: sdhci@e0101000 {
242                         compatible = "arasan,sdhci-8.9a";
243                         status = "disabled";
244                         clock-names = "clk_xin", "clk_ahb";
245                         clocks = <&clkc 22>, <&clkc 33>;
246                         interrupt-parent = <&intc>;
247                         interrupts = <0 47 4>;
248                         reg = <0xe0101000 0x1000>;
249                 };
250
251                 slcr: slcr@f8000000 {
252                         #address-cells = <1>;
253                         #size-cells = <1>;
254                         compatible = "xlnx,zynq-slcr", "syscon", "simple-bus";
255                         reg = <0xF8000000 0x1000>;
256                         ranges;
257                         clkc: clkc@100 {
258                                 #clock-cells = <1>;
259                                 compatible = "xlnx,ps7-clkc";
260                                 fclk-enable = <0>;
261                                 clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
262                                                 "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
263                                                 "dci", "lqspi", "smc", "pcap", "gem0", "gem1",
264                                                 "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
265                                                 "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
266                                                 "dma", "usb0_aper", "usb1_aper", "gem0_aper",
267                                                 "gem1_aper", "sdio0_aper", "sdio1_aper",
268                                                 "spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
269                                                 "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
270                                                 "gpio_aper", "lqspi_aper", "smc_aper", "swdt",
271                                                 "dbg_trc", "dbg_apb";
272                                 reg = <0x100 0x100>;
273                         };
274
275                         rstc: rstc@200 {
276                                 compatible = "xlnx,zynq-reset";
277                                 reg = <0x200 0x48>;
278                                 #reset-cells = <1>;
279                                 syscon = <&slcr>;
280                         };
281
282                         pinctrl0: pinctrl@700 {
283                                 compatible = "xlnx,pinctrl-zynq";
284                                 reg = <0x700 0x200>;
285                                 syscon = <&slcr>;
286                         };
287                 };
288
289                 dmac_s: dmac@f8003000 {
290                         compatible = "arm,pl330", "arm,primecell";
291                         reg = <0xf8003000 0x1000>;
292                         interrupt-parent = <&intc>;
293                         interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3",
294                                 "dma4", "dma5", "dma6", "dma7";
295                         interrupts = <0 13 4>,
296                                      <0 14 4>, <0 15 4>,
297                                      <0 16 4>, <0 17 4>,
298                                      <0 40 4>, <0 41 4>,
299                                      <0 42 4>, <0 43 4>;
300                         #dma-cells = <1>;
301                         #dma-channels = <8>;
302                         #dma-requests = <4>;
303                         clocks = <&clkc 27>;
304                         clock-names = "apb_pclk";
305                 };
306
307                 devcfg: devcfg@f8007000 {
308                         compatible = "xlnx,zynq-devcfg-1.0";
309                         interrupt-parent = <&intc>;
310                         interrupts = <0 8 4>;
311                         reg = <0xf8007000 0x100>;
312                         clocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>;
313                         clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3";
314                         syscon = <&slcr>;
315                 };
316
317                 global_timer: timer@f8f00200 {
318                         compatible = "arm,cortex-a9-global-timer";
319                         reg = <0xf8f00200 0x20>;
320                         interrupts = <1 11 0x301>;
321                         interrupt-parent = <&intc>;
322                         clocks = <&clkc 4>;
323                 };
324
325                 ttc0: timer@f8001000 {
326                         interrupt-parent = <&intc>;
327                         interrupts = <0 10 4>, <0 11 4>, <0 12 4>;
328                         compatible = "cdns,ttc";
329                         clocks = <&clkc 6>;
330                         reg = <0xF8001000 0x1000>;
331                 };
332
333                 ttc1: timer@f8002000 {
334                         interrupt-parent = <&intc>;
335                         interrupts = <0 37 4>, <0 38 4>, <0 39 4>;
336                         compatible = "cdns,ttc";
337                         clocks = <&clkc 6>;
338                         reg = <0xF8002000 0x1000>;
339                 };
340
341                 scutimer: timer@f8f00600 {
342                         interrupt-parent = <&intc>;
343                         interrupts = <1 13 0x301>;
344                         compatible = "arm,cortex-a9-twd-timer";
345                         reg = <0xf8f00600 0x20>;
346                         clocks = <&clkc 4>;
347                 };
348
349                 usb0: usb@e0002000 {
350                         compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
351                         status = "disabled";
352                         clocks = <&clkc 28>;
353                         interrupt-parent = <&intc>;
354                         interrupts = <0 21 4>;
355                         reg = <0xe0002000 0x1000>;
356                         phy_type = "ulpi";
357                 };
358
359                 usb1: usb@e0003000 {
360                         compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
361                         status = "disabled";
362                         clocks = <&clkc 29>;
363                         interrupt-parent = <&intc>;
364                         interrupts = <0 44 4>;
365                         reg = <0xe0003000 0x1000>;
366                         phy_type = "ulpi";
367                 };
368
369                 watchdog0: watchdog@f8005000 {
370                         clocks = <&clkc 45>;
371                         compatible = "cdns,wdt-r1p2";
372                         interrupt-parent = <&intc>;
373                         interrupts = <0 9 1>;
374                         reg = <0xf8005000 0x1000>;
375                         timeout-sec = <10>;
376                 };
377         };
378 };