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1 /*
2  * Xilinx Zynq 7000 DTSI
3  * Describes the hardware common to all Zynq 7000-based boards.
4  *
5  *  Copyright (C) 2011 - 2015 Xilinx
6  *
7  * SPDX-License-Identifier:     GPL-2.0+
8  */
9
10 / {
11         #address-cells = <1>;
12         #size-cells = <1>;
13         compatible = "xlnx,zynq-7000";
14
15         cpus {
16                 #address-cells = <1>;
17                 #size-cells = <0>;
18
19                 cpu0: cpu@0 {
20                         compatible = "arm,cortex-a9";
21                         device_type = "cpu";
22                         reg = <0>;
23                         clocks = <&clkc 3>;
24                         clock-latency = <1000>;
25                         cpu0-supply = <&regulator_vccpint>;
26                         operating-points = <
27                                 /* kHz    uV */
28                                 666667  1000000
29                                 333334  1000000
30                         >;
31                 };
32
33                 cpu1: cpu@1 {
34                         compatible = "arm,cortex-a9";
35                         device_type = "cpu";
36                         reg = <1>;
37                         clocks = <&clkc 3>;
38                 };
39         };
40
41         pmu@f8891000 {
42                 compatible = "arm,cortex-a9-pmu";
43                 interrupts = <0 5 4>, <0 6 4>;
44                 interrupt-parent = <&intc>;
45                 reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >;
46         };
47
48         regulator_vccpint: fixedregulator {
49                 compatible = "regulator-fixed";
50                 regulator-name = "VCCPINT";
51                 regulator-min-microvolt = <1000000>;
52                 regulator-max-microvolt = <1000000>;
53                 regulator-boot-on;
54                 regulator-always-on;
55         };
56
57         amba: amba {
58                 u-boot,dm-pre-reloc;
59                 compatible = "simple-bus";
60                 #address-cells = <1>;
61                 #size-cells = <1>;
62                 interrupt-parent = <&intc>;
63                 ranges;
64
65                 adc: adc@f8007100 {
66                         compatible = "xlnx,zynq-xadc-1.00.a";
67                         reg = <0xf8007100 0x20>;
68                         interrupts = <0 7 4>;
69                         interrupt-parent = <&intc>;
70                         clocks = <&clkc 12>;
71                 };
72
73                 can0: can@e0008000 {
74                         compatible = "xlnx,zynq-can-1.0";
75                         status = "disabled";
76                         clocks = <&clkc 19>, <&clkc 36>;
77                         clock-names = "can_clk", "pclk";
78                         reg = <0xe0008000 0x1000>;
79                         interrupts = <0 28 4>;
80                         interrupt-parent = <&intc>;
81                         tx-fifo-depth = <0x40>;
82                         rx-fifo-depth = <0x40>;
83                 };
84
85                 can1: can@e0009000 {
86                         compatible = "xlnx,zynq-can-1.0";
87                         status = "disabled";
88                         clocks = <&clkc 20>, <&clkc 37>;
89                         clock-names = "can_clk", "pclk";
90                         reg = <0xe0009000 0x1000>;
91                         interrupts = <0 51 4>;
92                         interrupt-parent = <&intc>;
93                         tx-fifo-depth = <0x40>;
94                         rx-fifo-depth = <0x40>;
95                 };
96
97                 gpio0: gpio@e000a000 {
98                         compatible = "xlnx,zynq-gpio-1.0";
99                         #gpio-cells = <2>;
100                         #interrupt-cells = <2>;
101                         clocks = <&clkc 42>;
102                         gpio-controller;
103                         interrupt-controller;
104                         interrupt-parent = <&intc>;
105                         interrupts = <0 20 4>;
106                         reg = <0xe000a000 0x1000>;
107                 };
108
109                 i2c0: i2c@e0004000 {
110                         compatible = "cdns,i2c-r1p10";
111                         status = "disabled";
112                         clocks = <&clkc 38>;
113                         interrupt-parent = <&intc>;
114                         interrupts = <0 25 4>;
115                         reg = <0xe0004000 0x1000>;
116                         #address-cells = <1>;
117                         #size-cells = <0>;
118                 };
119
120                 i2c1: i2c@e0005000 {
121                         compatible = "cdns,i2c-r1p10";
122                         status = "disabled";
123                         clocks = <&clkc 39>;
124                         interrupt-parent = <&intc>;
125                         interrupts = <0 48 4>;
126                         reg = <0xe0005000 0x1000>;
127                         #address-cells = <1>;
128                         #size-cells = <0>;
129                 };
130
131                 intc: interrupt-controller@f8f01000 {
132                         compatible = "arm,cortex-a9-gic";
133                         #interrupt-cells = <3>;
134                         interrupt-controller;
135                         reg = <0xF8F01000 0x1000>,
136                               <0xF8F00100 0x100>;
137                 };
138
139                 L2: cache-controller@f8f02000 {
140                         compatible = "arm,pl310-cache";
141                         reg = <0xF8F02000 0x1000>;
142                         interrupts = <0 2 4>;
143                         arm,data-latency = <3 2 2>;
144                         arm,tag-latency = <2 2 2>;
145                         cache-unified;
146                         cache-level = <2>;
147                 };
148
149                 mc: memory-controller@f8006000 {
150                         compatible = "xlnx,zynq-ddrc-a05";
151                         reg = <0xf8006000 0x1000>;
152                 };
153
154                 uart0: serial@e0000000 {
155                         compatible = "xlnx,xuartps", "cdns,uart-r1p8";
156                         status = "disabled";
157                         clocks = <&clkc 23>, <&clkc 40>;
158                         clock-names = "uart_clk", "pclk";
159                         reg = <0xE0000000 0x1000>;
160                         interrupts = <0 27 4>;
161                 };
162
163                 uart1: serial@e0001000 {
164                         compatible = "xlnx,xuartps", "cdns,uart-r1p8";
165                         status = "disabled";
166                         clocks = <&clkc 24>, <&clkc 41>;
167                         clock-names = "uart_clk", "pclk";
168                         reg = <0xE0001000 0x1000>;
169                         interrupts = <0 50 4>;
170                 };
171
172                 spi0: spi@e0006000 {
173                         compatible = "xlnx,zynq-spi-r1p6";
174                         reg = <0xe0006000 0x1000>;
175                         status = "disabled";
176                         interrupt-parent = <&intc>;
177                         interrupts = <0 26 4>;
178                         clocks = <&clkc 25>, <&clkc 34>;
179                         clock-names = "ref_clk", "pclk";
180                         #address-cells = <1>;
181                         #size-cells = <0>;
182                 };
183
184                 spi1: spi@e0007000 {
185                         compatible = "xlnx,zynq-spi-r1p6";
186                         reg = <0xe0007000 0x1000>;
187                         status = "disabled";
188                         interrupt-parent = <&intc>;
189                         interrupts = <0 49 4>;
190                         clocks = <&clkc 26>, <&clkc 35>;
191                         clock-names = "ref_clk", "pclk";
192                         #address-cells = <1>;
193                         #size-cells = <0>;
194                 };
195
196                 qspi: spi@e000d000 {
197                         clock-names = "ref_clk", "pclk";
198                         clocks = <&clkc 10>, <&clkc 43>;
199                         compatible = "xlnx,zynq-qspi-1.0";
200                         status = "disabled";
201                         interrupt-parent = <&intc>;
202                         interrupts = <0 19 4>;
203                         reg = <0xe000d000 0x1000>;
204                         #address-cells = <1>;
205                         #size-cells = <0>;
206                 };
207
208                 gem0: ethernet@e000b000 {
209                         compatible = "cdns,zynq-gem", "cdns,gem";
210                         reg = <0xe000b000 0x1000>;
211                         status = "disabled";
212                         interrupts = <0 22 4>;
213                         clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
214                         clock-names = "pclk", "hclk", "tx_clk";
215                         #address-cells = <1>;
216                         #size-cells = <0>;
217                 };
218
219                 gem1: ethernet@e000c000 {
220                         compatible = "cdns,zynq-gem", "cdns,gem";
221                         reg = <0xe000c000 0x1000>;
222                         status = "disabled";
223                         interrupts = <0 45 4>;
224                         clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;
225                         clock-names = "pclk", "hclk", "tx_clk";
226                         #address-cells = <1>;
227                         #size-cells = <0>;
228                 };
229
230                 sdhci0: sdhci@e0100000 {
231                         compatible = "arasan,sdhci-8.9a";
232                         status = "disabled";
233                         clock-names = "clk_xin", "clk_ahb";
234                         clocks = <&clkc 21>, <&clkc 32>;
235                         interrupt-parent = <&intc>;
236                         interrupts = <0 24 4>;
237                         reg = <0xe0100000 0x1000>;
238                 };
239
240                 sdhci1: sdhci@e0101000 {
241                         compatible = "arasan,sdhci-8.9a";
242                         status = "disabled";
243                         clock-names = "clk_xin", "clk_ahb";
244                         clocks = <&clkc 22>, <&clkc 33>;
245                         interrupt-parent = <&intc>;
246                         interrupts = <0 47 4>;
247                         reg = <0xe0101000 0x1000>;
248                 };
249
250                 slcr: slcr@f8000000 {
251                         #address-cells = <1>;
252                         #size-cells = <1>;
253                         compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd";
254                         reg = <0xF8000000 0x1000>;
255                         ranges;
256                         clkc: clkc@100 {
257                                 #clock-cells = <1>;
258                                 compatible = "xlnx,ps7-clkc";
259                                 fclk-enable = <0>;
260                                 clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
261                                                 "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
262                                                 "dci", "lqspi", "smc", "pcap", "gem0", "gem1",
263                                                 "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
264                                                 "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
265                                                 "dma", "usb0_aper", "usb1_aper", "gem0_aper",
266                                                 "gem1_aper", "sdio0_aper", "sdio1_aper",
267                                                 "spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
268                                                 "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
269                                                 "gpio_aper", "lqspi_aper", "smc_aper", "swdt",
270                                                 "dbg_trc", "dbg_apb";
271                                 reg = <0x100 0x100>;
272                         };
273
274                         rstc: rstc@200 {
275                                 compatible = "xlnx,zynq-reset";
276                                 reg = <0x200 0x48>;
277                                 #reset-cells = <1>;
278                                 syscon = <&slcr>;
279                         };
280
281                         pinctrl0: pinctrl@700 {
282                                 compatible = "xlnx,pinctrl-zynq";
283                                 reg = <0x700 0x200>;
284                                 syscon = <&slcr>;
285                         };
286                 };
287
288                 dmac_s: dmac@f8003000 {
289                         compatible = "arm,pl330", "arm,primecell";
290                         reg = <0xf8003000 0x1000>;
291                         interrupt-parent = <&intc>;
292                         interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3",
293                                 "dma4", "dma5", "dma6", "dma7";
294                         interrupts = <0 13 4>,
295                                      <0 14 4>, <0 15 4>,
296                                      <0 16 4>, <0 17 4>,
297                                      <0 40 4>, <0 41 4>,
298                                      <0 42 4>, <0 43 4>;
299                         #dma-cells = <1>;
300                         #dma-channels = <8>;
301                         #dma-requests = <4>;
302                         clocks = <&clkc 27>;
303                         clock-names = "apb_pclk";
304                 };
305
306                 devcfg: devcfg@f8007000 {
307                         compatible = "xlnx,zynq-devcfg-1.0";
308                         interrupt-parent = <&intc>;
309                         interrupts = <0 8 4>;
310                         reg = <0xf8007000 0x100>;
311                         clocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>;
312                         clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3";
313                         syscon = <&slcr>;
314                 };
315
316                 global_timer: timer@f8f00200 {
317                         compatible = "arm,cortex-a9-global-timer";
318                         reg = <0xf8f00200 0x20>;
319                         interrupts = <1 11 0x301>;
320                         interrupt-parent = <&intc>;
321                         clocks = <&clkc 4>;
322                 };
323
324                 ttc0: timer@f8001000 {
325                         interrupt-parent = <&intc>;
326                         interrupts = <0 10 4>, <0 11 4>, <0 12 4>;
327                         compatible = "cdns,ttc";
328                         clocks = <&clkc 6>;
329                         reg = <0xF8001000 0x1000>;
330                 };
331
332                 ttc1: timer@f8002000 {
333                         interrupt-parent = <&intc>;
334                         interrupts = <0 37 4>, <0 38 4>, <0 39 4>;
335                         compatible = "cdns,ttc";
336                         clocks = <&clkc 6>;
337                         reg = <0xF8002000 0x1000>;
338                 };
339
340                 scutimer: timer@f8f00600 {
341                         interrupt-parent = <&intc>;
342                         interrupts = <1 13 0x301>;
343                         compatible = "arm,cortex-a9-twd-timer";
344                         reg = <0xf8f00600 0x20>;
345                         clocks = <&clkc 4>;
346                 };
347
348                 usb0: usb@e0002000 {
349                         compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
350                         status = "disabled";
351                         clocks = <&clkc 28>;
352                         interrupt-parent = <&intc>;
353                         interrupts = <0 21 4>;
354                         reg = <0xe0002000 0x1000>;
355                         phy_type = "ulpi";
356                 };
357
358                 usb1: usb@e0003000 {
359                         compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
360                         status = "disabled";
361                         clocks = <&clkc 29>;
362                         interrupt-parent = <&intc>;
363                         interrupts = <0 44 4>;
364                         reg = <0xe0003000 0x1000>;
365                         phy_type = "ulpi";
366                 };
367
368                 watchdog0: watchdog@f8005000 {
369                         clocks = <&clkc 45>;
370                         compatible = "cdns,wdt-r1p2";
371                         interrupt-parent = <&intc>;
372                         interrupts = <0 9 1>;
373                         reg = <0xf8005000 0x1000>;
374                         timeout-sec = <10>;
375                 };
376         };
377 };