2 * Xilinx Zynq 7000 DTSI
3 * Describes the hardware common to all Zynq 7000-based boards.
5 * Copyright (C) 2011 - 2015 Xilinx
7 * SPDX-License-Identifier: GPL-2.0+
9 /include/ "skeleton.dtsi"
12 compatible = "xlnx,zynq-7000";
19 compatible = "arm,cortex-a9";
23 clock-latency = <1000>;
24 cpu0-supply = <®ulator_vccpint>;
33 compatible = "arm,cortex-a9";
41 compatible = "arm,cortex-a9-pmu";
42 interrupts = <0 5 4>, <0 6 4>;
43 interrupt-parent = <&intc>;
44 reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >;
47 regulator_vccpint: fixedregulator@0 {
48 compatible = "regulator-fixed";
49 regulator-name = "VCCPINT";
50 regulator-min-microvolt = <1000000>;
51 regulator-max-microvolt = <1000000>;
57 compatible = "simple-bus";
60 interrupt-parent = <&intc>;
64 compatible = "xlnx,zynq-xadc-1.00.a";
65 reg = <0xf8007100 0x20>;
67 interrupt-parent = <&intc>;
72 compatible = "xlnx,zynq-can-1.0";
74 clocks = <&clkc 19>, <&clkc 36>;
75 clock-names = "can_clk", "pclk";
76 reg = <0xe0008000 0x1000>;
77 interrupts = <0 28 4>;
78 interrupt-parent = <&intc>;
79 tx-fifo-depth = <0x40>;
80 rx-fifo-depth = <0x40>;
84 compatible = "xlnx,zynq-can-1.0";
86 clocks = <&clkc 20>, <&clkc 37>;
87 clock-names = "can_clk", "pclk";
88 reg = <0xe0009000 0x1000>;
89 interrupts = <0 51 4>;
90 interrupt-parent = <&intc>;
91 tx-fifo-depth = <0x40>;
92 rx-fifo-depth = <0x40>;
95 gpio0: gpio@e000a000 {
96 compatible = "xlnx,zynq-gpio-1.0";
100 interrupt-parent = <&intc>;
101 interrupts = <0 20 4>;
102 reg = <0xe000a000 0x1000>;
106 compatible = "cdns,i2c-r1p10";
109 interrupt-parent = <&intc>;
110 interrupts = <0 25 4>;
111 reg = <0xe0004000 0x1000>;
112 #address-cells = <1>;
117 compatible = "cdns,i2c-r1p10";
120 interrupt-parent = <&intc>;
121 interrupts = <0 48 4>;
122 reg = <0xe0005000 0x1000>;
123 #address-cells = <1>;
127 intc: interrupt-controller@f8f01000 {
128 compatible = "arm,cortex-a9-gic";
129 #interrupt-cells = <3>;
130 interrupt-controller;
131 reg = <0xF8F01000 0x1000>,
135 L2: cache-controller@f8f02000 {
136 compatible = "arm,pl310-cache";
137 reg = <0xF8F02000 0x1000>;
138 interrupts = <0 2 4>;
139 arm,data-latency = <3 2 2>;
140 arm,tag-latency = <2 2 2>;
145 mc: memory-controller@f8006000 {
146 compatible = "xlnx,zynq-ddrc-a05";
147 reg = <0xf8006000 0x1000>;
150 uart0: serial@e0000000 {
151 compatible = "xlnx,xuartps", "cdns,uart-r1p8";
153 clocks = <&clkc 23>, <&clkc 40>;
154 clock-names = "uart_clk", "pclk";
155 reg = <0xE0000000 0x1000>;
156 interrupts = <0 27 4>;
159 uart1: serial@e0001000 {
160 compatible = "xlnx,xuartps", "cdns,uart-r1p8";
162 clocks = <&clkc 24>, <&clkc 41>;
163 clock-names = "uart_clk", "pclk";
164 reg = <0xE0001000 0x1000>;
165 interrupts = <0 50 4>;
169 compatible = "xlnx,zynq-spi-r1p6";
170 reg = <0xe0006000 0x1000>;
172 interrupt-parent = <&intc>;
173 interrupts = <0 26 4>;
174 clocks = <&clkc 25>, <&clkc 34>;
175 clock-names = "ref_clk", "pclk";
176 spi-max-frequency = <166666700>;
177 #address-cells = <1>;
182 compatible = "xlnx,zynq-spi-r1p6";
183 reg = <0xe0007000 0x1000>;
185 interrupt-parent = <&intc>;
186 interrupts = <0 49 4>;
187 clocks = <&clkc 26>, <&clkc 35>;
188 clock-names = "ref_clk", "pclk";
189 spi-max-frequency = <166666700>;
190 #address-cells = <1>;
195 clock-names = "ref_clk", "pclk";
196 clocks = <&clkc 10>, <&clkc 43>;
197 compatible = "xlnx,zynq-qspi-1.0";
199 interrupt-parent = <&intc>;
200 interrupts = <0 19 4>;
201 reg = <0xe000d000 0x1000>;
202 #address-cells = <1>;
206 gem0: ethernet@e000b000 {
207 compatible = "cdns,zynq-gem", "cdns,gem";
208 reg = <0xe000b000 0x1000>;
210 interrupts = <0 22 4>;
211 clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
212 clock-names = "pclk", "hclk", "tx_clk";
213 #address-cells = <1>;
217 gem1: ethernet@e000c000 {
218 compatible = "cdns,zynq-gem", "cdns,gem";
219 reg = <0xe000c000 0x1000>;
221 interrupts = <0 45 4>;
222 clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;
223 clock-names = "pclk", "hclk", "tx_clk";
224 #address-cells = <1>;
228 sdhci0: sdhci@e0100000 {
229 compatible = "arasan,sdhci-8.9a";
231 clock-names = "clk_xin", "clk_ahb";
232 clocks = <&clkc 21>, <&clkc 32>;
233 interrupt-parent = <&intc>;
234 interrupts = <0 24 4>;
235 reg = <0xe0100000 0x1000>;
238 sdhci1: sdhci@e0101000 {
239 compatible = "arasan,sdhci-8.9a";
241 clock-names = "clk_xin", "clk_ahb";
242 clocks = <&clkc 22>, <&clkc 33>;
243 interrupt-parent = <&intc>;
244 interrupts = <0 47 4>;
245 reg = <0xe0101000 0x1000>;
248 slcr: slcr@f8000000 {
249 #address-cells = <1>;
251 compatible = "xlnx,zynq-slcr", "syscon", "simple-bus";
252 reg = <0xF8000000 0x1000>;
256 compatible = "xlnx,ps7-clkc";
258 clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
259 "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
260 "dci", "lqspi", "smc", "pcap", "gem0", "gem1",
261 "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
262 "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
263 "dma", "usb0_aper", "usb1_aper", "gem0_aper",
264 "gem1_aper", "sdio0_aper", "sdio1_aper",
265 "spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
266 "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
267 "gpio_aper", "lqspi_aper", "smc_aper", "swdt",
268 "dbg_trc", "dbg_apb";
272 pinctrl0: pinctrl@700 {
273 compatible = "xlnx,pinctrl-zynq";
279 dmac_s: dmac@f8003000 {
280 compatible = "arm,pl330", "arm,primecell";
281 reg = <0xf8003000 0x1000>;
282 interrupt-parent = <&intc>;
283 interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3",
284 "dma4", "dma5", "dma6", "dma7";
285 interrupts = <0 13 4>,
294 clock-names = "apb_pclk";
297 devcfg: devcfg@f8007000 {
298 compatible = "xlnx,zynq-devcfg-1.0";
299 reg = <0xf8007000 0x100>;
302 global_timer: timer@f8f00200 {
303 compatible = "arm,cortex-a9-global-timer";
304 reg = <0xf8f00200 0x20>;
305 interrupts = <1 11 0x301>;
306 interrupt-parent = <&intc>;
310 ttc0: timer@f8001000 {
311 interrupt-parent = <&intc>;
312 interrupts = <0 10 4>, <0 11 4>, <0 12 4>;
313 compatible = "cdns,ttc";
315 reg = <0xF8001000 0x1000>;
318 ttc1: timer@f8002000 {
319 interrupt-parent = <&intc>;
320 interrupts = <0 37 4>, <0 38 4>, <0 39 4>;
321 compatible = "cdns,ttc";
323 reg = <0xF8002000 0x1000>;
326 scutimer: timer@f8f00600 {
327 interrupt-parent = <&intc>;
328 interrupts = < 1 13 0x301 >;
329 compatible = "arm,cortex-a9-twd-timer";
330 reg = < 0xf8f00600 0x20 >;
335 compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
338 interrupt-parent = <&intc>;
339 interrupts = <0 21 4>;
340 reg = <0xe0002000 0x1000>;
345 compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
348 interrupt-parent = <&intc>;
349 interrupts = <0 44 4>;
350 reg = <0xe0003000 0x1000>;
354 watchdog0: watchdog@f8005000 {
356 compatible = "cdns,wdt-r1p2";
357 interrupt-parent = <&intc>;
358 interrupts = <0 9 1>;
359 reg = <0xf8005000 0x1000>;