git.sur5r.net Git - u-boot/blob - arch/arm/dts/zynq-7000.dtsi

   1 /*
   2  * Xilinx Zynq 7000 DTSI
   3  * Describes the hardware common to all Zynq 7000-based boards.
   4  *
   5  * Copyright (C) 2013 Xilinx, Inc.
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9 /include/ "skeleton.dtsi"
  10
  11 / {
  12         compatible = "xlnx,zynq-7000";
  13
  14         cpus {
  15                 #address-cells = <1>;
  16                 #size-cells = <0>;
  17
  18                 cpu@0 {
  19                         compatible = "arm,cortex-a9";
  20                         device_type = "cpu";
  21                         reg = <0>;
  22                         clocks = <&clkc 3>;
  23                         clock-latency = <1000>;
  24                         cpu0-supply = <&regulator_vccpint>;
  25                         operating-points = <
  26                                 /* kHz    uV */
  27                                 666667  1000000
  28                                 333334  1000000
  29                                 222223  1000000
  30                         >;
  31                 };
  32
  33                 cpu@1 {
  34                         compatible = "arm,cortex-a9";
  35                         device_type = "cpu";
  36                         reg = <1>;
  37                         clocks = <&clkc 3>;
  38                 };
  39         };
  40
  41         pmu {
  42                 compatible = "arm,cortex-a9-pmu";
  43                 interrupts = <0 5 4>, <0 6 4>;
  44                 interrupt-parent = <&intc>;
  45                 reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >;
  46         };
  47
  48         regulator_vccpint: fixedregulator@0 {
  49                 compatible = "regulator-fixed";
  50                 regulator-name = "VCCPINT";
  51                 regulator-min-microvolt = <1000000>;
  52                 regulator-max-microvolt = <1000000>;
  53                 regulator-boot-on;
  54                 regulator-always-on;
  55         };
  56
  57         amba {
  58                 compatible = "simple-bus";
  59                 #address-cells = <1>;
  60                 #size-cells = <1>;
  61                 interrupt-parent = <&intc>;
  62                 ranges;
  63
  64                 adc: adc@f8007100 {
  65                         compatible = "xlnx,zynq-xadc-1.00.a";
  66                         reg = <0xf8007100 0x20>;
  67                         interrupts = <0 7 4>;
  68                         interrupt-parent = <&intc>;
  69                         clocks = <&clkc 12>;
  70                 };
  71
  72                 can0: can@e0008000 {
  73                         compatible = "xlnx,zynq-can-1.0";
  74                         status = "disabled";
  75                         clocks = <&clkc 19>, <&clkc 36>;
  76                         clock-names = "can_clk", "pclk";
  77                         reg = <0xe0008000 0x1000>;
  78                         interrupts = <0 28 4>;
  79                         interrupt-parent = <&intc>;
  80                         tx-fifo-depth = <0x40>;
  81                         rx-fifo-depth = <0x40>;
  82                 };
  83
  84                 can1: can@e0009000 {
  85                         compatible = "xlnx,zynq-can-1.0";
  86                         status = "disabled";
  87                         clocks = <&clkc 20>, <&clkc 37>;
  88                         clock-names = "can_clk", "pclk";
  89                         reg = <0xe0009000 0x1000>;
  90                         interrupts = <0 51 4>;
  91                         interrupt-parent = <&intc>;
  92                         tx-fifo-depth = <0x40>;
  93                         rx-fifo-depth = <0x40>;
  94                 };
  95
  96                 gpio0: gpio@e000a000 {
  97                         compatible = "xlnx,zynq-gpio-1.0";
  98                         #gpio-cells = <2>;
  99                         clocks = <&clkc 42>;
 100                         gpio-controller;
 101                         interrupt-parent = <&intc>;
 102                         interrupts = <0 20 4>;
 103                         reg = <0xe000a000 0x1000>;
 104                 };
 105
 106                 i2c0: i2c@e0004000 {
 107                         compatible = "cdns,i2c-r1p10";
 108                         status = "disabled";
 109                         clocks = <&clkc 38>;
 110                         interrupt-parent = <&intc>;
 111                         interrupts = <0 25 4>;
 112                         reg = <0xe0004000 0x1000>;
 113                         #address-cells = <1>;
 114                         #size-cells = <0>;
 115                 };
 116
 117                 i2c1: i2c@e0005000 {
 118                         compatible = "cdns,i2c-r1p10";
 119                         status = "disabled";
 120                         clocks = <&clkc 39>;
 121                         interrupt-parent = <&intc>;
 122                         interrupts = <0 48 4>;
 123                         reg = <0xe0005000 0x1000>;
 124                         #address-cells = <1>;
 125                         #size-cells = <0>;
 126                 };
 127
 128                 intc: interrupt-controller@f8f01000 {
 129                         compatible = "arm,cortex-a9-gic";
 130                         #interrupt-cells = <3>;
 131                         #address-cells = <1>;
 132                         interrupt-controller;
 133                         reg = <0xF8F01000 0x1000>,
 134                               <0xF8F00100 0x100>;
 135                 };
 136
 137                 L2: cache-controller@f8f02000 {
 138                         compatible = "arm,pl310-cache";
 139                         reg = <0xF8F02000 0x1000>;
 140                         arm,data-latency = <3 2 2>;
 141                         arm,tag-latency = <2 2 2>;
 142                         cache-unified;
 143                         cache-level = <2>;
 144                 };
 145
 146                 mc: memory-controller@f8006000 {
 147                         compatible = "xlnx,zynq-ddrc-a05";
 148                         reg = <0xf8006000 0x1000>;
 149                 };
 150
 151                 uart0: serial@e0000000 {
 152                         compatible = "xlnx,xuartps";
 153                         status = "disabled";
 154                         clocks = <&clkc 23>, <&clkc 40>;
 155                         clock-names = "ref_clk", "aper_clk";
 156                         reg = <0xE0000000 0x1000>;
 157                         interrupts = <0 27 4>;
 158                 };
 159
 160                 uart1: serial@e0001000 {
 161                         compatible = "xlnx,xuartps";
 162                         status = "disabled";
 163                         clocks = <&clkc 24>, <&clkc 41>;
 164                         clock-names = "ref_clk", "aper_clk";
 165                         reg = <0xE0001000 0x1000>;
 166                         interrupts = <0 50 4>;
 167                 };
 168
 169                 spi0: spi@e0006000 {
 170                         compatible = "xlnx,zynq-spi";
 171                         reg = <0xe0006000 0x1000>;
 172                         status = "disabled";
 173                         interrupt-parent = <&intc>;
 174                         interrupts = <0 26 4>;
 175                         clocks = <&clkc 25>, <&clkc 34>;
 176                         clock-names = "ref_clk", "pclk";
 177                         spi-max-frequency = <166666700>;
 178                         #address-cells = <1>;
 179                         #size-cells = <0>;
 180                 };
 181
 182                 spi1: spi@e0007000 {
 183                         compatible = "xlnx,zynq-spi";
 184                         reg = <0xe0007000 0x1000>;
 185                         status = "disabled";
 186                         interrupt-parent = <&intc>;
 187                         interrupts = <0 49 4>;
 188                         clocks = <&clkc 26>, <&clkc 35>;
 189                         clock-names = "ref_clk", "pclk";
 190                         spi-max-frequency = <166666700>;
 191                         #address-cells = <1>;
 192                         #size-cells = <0>;
 193                 };
 194
 195                 gem0: ethernet@e000b000 {
 196                         compatible = "cdns,gem";
 197                         reg = <0xe000b000 0x4000>;
 198                         status = "disabled";
 199                         interrupts = <0 22 4>;
 200                         clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
 201                         clock-names = "pclk", "hclk", "tx_clk";
 202                 };
 203
 204                 gem1: ethernet@e000c000 {
 205                         compatible = "cdns,gem";
 206                         reg = <0xe000c000 0x4000>;
 207                         status = "disabled";
 208                         interrupts = <0 45 4>;
 209                         clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;
 210                         clock-names = "pclk", "hclk", "tx_clk";
 211                 };
 212
 213                 sdhci0: sdhci@e0100000 {
 214                         compatible = "arasan,sdhci-8.9a";
 215                         status = "disabled";
 216                         clock-names = "clk_xin", "clk_ahb";
 217                         clocks = <&clkc 21>, <&clkc 32>;
 218                         interrupt-parent = <&intc>;
 219                         interrupts = <0 24 4>;
 220                         reg = <0xe0100000 0x1000>;
 221                 } ;
 222
 223                 sdhci1: sdhci@e0101000 {
 224                         compatible = "arasan,sdhci-8.9a";
 225                         status = "disabled";
 226                         clock-names = "clk_xin", "clk_ahb";
 227                         clocks = <&clkc 22>, <&clkc 33>;
 228                         interrupt-parent = <&intc>;
 229                         interrupts = <0 47 4>;
 230                         reg = <0xe0101000 0x1000>;
 231                 } ;
 232
 233                 slcr: slcr@f8000000 {
 234                         #address-cells = <1>;
 235                         #size-cells = <1>;
 236                         compatible = "xlnx,zynq-slcr", "syscon";
 237                         reg = <0xF8000000 0x1000>;
 238                         ranges;
 239                         clkc: clkc@100 {
 240                                 #clock-cells = <1>;
 241                                 compatible = "xlnx,ps7-clkc";
 242                                 ps-clk-frequency = <33333333>;
 243                                 fclk-enable = <0>;
 244                                 clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
 245                                                 "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
 246                                                 "dci", "lqspi", "smc", "pcap", "gem0", "gem1",
 247                                                 "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
 248                                                 "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
 249                                                 "dma", "usb0_aper", "usb1_aper", "gem0_aper",
 250                                                 "gem1_aper", "sdio0_aper", "sdio1_aper",
 251                                                 "spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
 252                                                 "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
 253                                                 "gpio_aper", "lqspi_aper", "smc_aper", "swdt",
 254                                                 "dbg_trc", "dbg_apb";
 255                                 reg = <0x100 0x100>;
 256                         };
 257                 };
 258
 259                 dmac_s: dmac@f8003000 {
 260                         compatible = "arm,pl330", "arm,primecell";
 261                         reg = <0xf8003000 0x1000>;
 262                         interrupt-parent = <&intc>;
 263                         interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3",
 264                                 "dma4", "dma5", "dma6", "dma7";
 265                         interrupts = <0 13 4>,
 266                                      <0 14 4>, <0 15 4>,
 267                                      <0 16 4>, <0 17 4>,
 268                                      <0 40 4>, <0 41 4>,
 269                                      <0 42 4>, <0 43 4>;
 270                         #dma-cells = <1>;
 271                         #dma-channels = <8>;
 272                         #dma-requests = <4>;
 273                         clocks = <&clkc 27>;
 274                         clock-names = "apb_pclk";
 275                 };
 276
 277                 devcfg: devcfg@f8007000 {
 278                         compatible = "xlnx,zynq-devcfg-1.0";
 279                         reg = <0xf8007000 0x100>;
 280                 };
 281
 282                 global_timer: timer@f8f00200 {
 283                         compatible = "arm,cortex-a9-global-timer";
 284                         reg = <0xf8f00200 0x20>;
 285                         interrupts = <1 11 0x301>;
 286                         interrupt-parent = <&intc>;
 287                         clocks = <&clkc 4>;
 288                 };
 289
 290                 ttc0: timer@f8001000 {
 291                         interrupt-parent = <&intc>;
 292                         interrupts = < 0 10 4 0 11 4 0 12 4 >;
 293                         compatible = "cdns,ttc";
 294                         clocks = <&clkc 6>;
 295                         reg = <0xF8001000 0x1000>;
 296                 };
 297
 298                 ttc1: timer@f8002000 {
 299                         interrupt-parent = <&intc>;
 300                         interrupts = < 0 37 4 0 38 4 0 39 4 >;
 301                         compatible = "cdns,ttc";
 302                         clocks = <&clkc 6>;
 303                         reg = <0xF8002000 0x1000>;
 304                 };
 305
 306                 scutimer: timer@f8f00600 {
 307                         interrupt-parent = <&intc>;
 308                         interrupts = < 1 13 0x301 >;
 309                         compatible = "arm,cortex-a9-twd-timer";
 310                         reg = < 0xf8f00600 0x20 >;
 311                         clocks = <&clkc 4>;
 312                 } ;
 313
 314                 usb0: usb@e0002000 {
 315                         compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
 316                         status = "disabled";
 317                         clocks = <&clkc 28>;
 318                         interrupt-parent = <&intc>;
 319                         interrupts = <0 21 4>;
 320                         reg = <0xe0002000 0x1000>;
 321                         phy_type = "ulpi";
 322                 };
 323
 324                 usb1: usb@e0003000 {
 325                         compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
 326                         status = "disabled";
 327                         clocks = <&clkc 29>;
 328                         interrupt-parent = <&intc>;
 329                         interrupts = <0 44 4>;
 330                         reg = <0xe0003000 0x1000>;
 331                         phy_type = "ulpi";
 332                 };
 333
 334                 watchdog0: watchdog@f8005000 {
 335                         clocks = <&clkc 45>;
 336                         compatible = "cdns,wdt-r1p2";
 337                         interrupt-parent = <&intc>;
 338                         interrupts = <0 9 1>;
 339                         reg = <0xf8005000 0x1000>;
 340                         timeout-sec = <10>;
 341                 };
 342         };
 343 };