2 * Xilinx Zynq 7000 DTSI
3 * Describes the hardware common to all Zynq 7000-based boards.
5 * Copyright (C) 2013 Xilinx, Inc.
7 * SPDX-License-Identifier: GPL-2.0+
9 /include/ "skeleton.dtsi"
12 compatible = "xlnx,zynq-7000";
19 compatible = "arm,cortex-a9";
23 clock-latency = <1000>;
33 compatible = "arm,cortex-a9";
41 compatible = "arm,cortex-a9-pmu";
42 interrupts = <0 5 4>, <0 6 4>;
43 interrupt-parent = <&intc>;
44 reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >;
48 compatible = "simple-bus";
51 interrupt-parent = <&intc>;
55 compatible = "xlnx,zynq-xadc-1.00.a";
56 reg = <0xf8007100 0x20>;
58 interrupt-parent = <&intc>;
63 compatible = "xlnx,zynq-can-1.0";
65 clocks = <&clkc 19>, <&clkc 36>;
66 clock-names = "can_clk", "pclk";
67 reg = <0xe0008000 0x1000>;
68 interrupts = <0 28 4>;
69 interrupt-parent = <&intc>;
70 tx-fifo-depth = <0x40>;
71 rx-fifo-depth = <0x40>;
75 compatible = "xlnx,zynq-can-1.0";
77 clocks = <&clkc 20>, <&clkc 37>;
78 clock-names = "can_clk", "pclk";
79 reg = <0xe0009000 0x1000>;
80 interrupts = <0 51 4>;
81 interrupt-parent = <&intc>;
82 tx-fifo-depth = <0x40>;
83 rx-fifo-depth = <0x40>;
86 gpio0: gpio@e000a000 {
87 compatible = "xlnx,zynq-gpio-1.0";
91 interrupt-parent = <&intc>;
92 interrupts = <0 20 4>;
93 reg = <0xe000a000 0x1000>;
97 compatible = "cdns,i2c-r1p10";
100 interrupt-parent = <&intc>;
101 interrupts = <0 25 4>;
102 reg = <0xe0004000 0x1000>;
103 #address-cells = <1>;
108 compatible = "cdns,i2c-r1p10";
111 interrupt-parent = <&intc>;
112 interrupts = <0 48 4>;
113 reg = <0xe0005000 0x1000>;
114 #address-cells = <1>;
118 intc: interrupt-controller@f8f01000 {
119 compatible = "arm,cortex-a9-gic";
120 #interrupt-cells = <3>;
121 #address-cells = <1>;
122 interrupt-controller;
123 reg = <0xF8F01000 0x1000>,
127 L2: cache-controller@f8f02000 {
128 compatible = "arm,pl310-cache";
129 reg = <0xF8F02000 0x1000>;
130 arm,data-latency = <3 2 2>;
131 arm,tag-latency = <2 2 2>;
136 mc: memory-controller@f8006000 {
137 compatible = "xlnx,zynq-ddrc-a05";
138 reg = <0xf8006000 0x1000>;
141 uart0: serial@e0000000 {
142 compatible = "xlnx,xuartps";
144 clocks = <&clkc 23>, <&clkc 40>;
145 clock-names = "ref_clk", "aper_clk";
146 reg = <0xE0000000 0x1000>;
147 interrupts = <0 27 4>;
150 uart1: serial@e0001000 {
151 compatible = "xlnx,xuartps";
153 clocks = <&clkc 24>, <&clkc 41>;
154 clock-names = "ref_clk", "aper_clk";
155 reg = <0xE0001000 0x1000>;
156 interrupts = <0 50 4>;
160 compatible = "xlnx,zynq-spi";
161 reg = <0xe0006000 0x1000>;
163 interrupt-parent = <&intc>;
164 interrupts = <0 26 4>;
165 clocks = <&clkc 25>, <&clkc 34>;
166 clock-names = "ref_clk", "pclk";
167 spi-max-frequency = <166666700>;
168 #address-cells = <1>;
173 compatible = "xlnx,zynq-spi";
174 reg = <0xe0007000 0x1000>;
176 interrupt-parent = <&intc>;
177 interrupts = <0 49 4>;
178 clocks = <&clkc 26>, <&clkc 35>;
179 clock-names = "ref_clk", "pclk";
180 spi-max-frequency = <166666700>;
181 #address-cells = <1>;
185 gem0: ethernet@e000b000 {
186 compatible = "cdns,gem";
187 reg = <0xe000b000 0x4000>;
189 interrupts = <0 22 4>;
190 clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
191 clock-names = "pclk", "hclk", "tx_clk";
194 gem1: ethernet@e000c000 {
195 compatible = "cdns,gem";
196 reg = <0xe000c000 0x4000>;
198 interrupts = <0 45 4>;
199 clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;
200 clock-names = "pclk", "hclk", "tx_clk";
203 sdhci0: sdhci@e0100000 {
204 compatible = "arasan,sdhci-8.9a";
206 clock-names = "clk_xin", "clk_ahb";
207 clocks = <&clkc 21>, <&clkc 32>;
208 interrupt-parent = <&intc>;
209 interrupts = <0 24 4>;
210 reg = <0xe0100000 0x1000>;
213 sdhci1: sdhci@e0101000 {
214 compatible = "arasan,sdhci-8.9a";
216 clock-names = "clk_xin", "clk_ahb";
217 clocks = <&clkc 22>, <&clkc 33>;
218 interrupt-parent = <&intc>;
219 interrupts = <0 47 4>;
220 reg = <0xe0101000 0x1000>;
223 slcr: slcr@f8000000 {
224 #address-cells = <1>;
226 compatible = "xlnx,zynq-slcr", "syscon";
227 reg = <0xF8000000 0x1000>;
231 compatible = "xlnx,ps7-clkc";
232 ps-clk-frequency = <33333333>;
234 clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
235 "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
236 "dci", "lqspi", "smc", "pcap", "gem0", "gem1",
237 "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
238 "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
239 "dma", "usb0_aper", "usb1_aper", "gem0_aper",
240 "gem1_aper", "sdio0_aper", "sdio1_aper",
241 "spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
242 "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
243 "gpio_aper", "lqspi_aper", "smc_aper", "swdt",
244 "dbg_trc", "dbg_apb";
249 dmac_s: dmac@f8003000 {
250 compatible = "arm,pl330", "arm,primecell";
251 reg = <0xf8003000 0x1000>;
252 interrupt-parent = <&intc>;
253 interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3",
254 "dma4", "dma5", "dma6", "dma7";
255 interrupts = <0 13 4>,
264 clock-names = "apb_pclk";
267 devcfg: devcfg@f8007000 {
268 compatible = "xlnx,zynq-devcfg-1.0";
269 reg = <0xf8007000 0x100>;
272 global_timer: timer@f8f00200 {
273 compatible = "arm,cortex-a9-global-timer";
274 reg = <0xf8f00200 0x20>;
275 interrupts = <1 11 0x301>;
276 interrupt-parent = <&intc>;
280 ttc0: timer@f8001000 {
281 interrupt-parent = <&intc>;
282 interrupts = < 0 10 4 0 11 4 0 12 4 >;
283 compatible = "cdns,ttc";
285 reg = <0xF8001000 0x1000>;
288 ttc1: timer@f8002000 {
289 interrupt-parent = <&intc>;
290 interrupts = < 0 37 4 0 38 4 0 39 4 >;
291 compatible = "cdns,ttc";
293 reg = <0xF8002000 0x1000>;
296 scutimer: timer@f8f00600 {
297 interrupt-parent = <&intc>;
298 interrupts = < 1 13 0x301 >;
299 compatible = "arm,cortex-a9-twd-timer";
300 reg = < 0xf8f00600 0x20 >;
305 compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
308 interrupt-parent = <&intc>;
309 interrupts = <0 21 4>;
310 reg = <0xe0002000 0x1000>;
315 compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
318 interrupt-parent = <&intc>;
319 interrupts = <0 44 4>;
320 reg = <0xe0003000 0x1000>;
324 watchdog0: watchdog@f8005000 {
326 compatible = "cdns,wdt-r1p2";
327 interrupt-parent = <&intc>;
328 interrupts = <0 9 1>;
329 reg = <0xf8005000 0x1000>;