2 * Xilinx ZC702 board DTS
4 * Copyright (C) 2011 - 2015 Xilinx
5 * Copyright (C) 2012 National Instruments Corp.
7 * SPDX-License-Identifier: GPL-2.0+
10 #include "zynq-7000.dtsi"
13 model = "Zynq ZC702 Development Board";
14 compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000";
23 device_type = "memory";
24 reg = <0x0 0x40000000>;
28 bootargs = "earlyprintk";
29 stdout-path = "serial0:115200n8";
33 compatible = "gpio-leds";
37 gpios = <&gpio0 10 0>;
38 linux,default-trigger = "heartbeat";
43 compatible = "usb-nop-xceiv";
50 compatible = "mmio-sram";
51 reg = <0xfffc0000 0x10000>;
57 pinctrl-names = "default";
58 pinctrl-0 = <&pinctrl_can0_default>;
62 ps-clk-frequency = <33333333>;
67 phy-mode = "rgmii-id";
68 phy-handle = <ðernet_phy>;
69 pinctrl-names = "default";
70 pinctrl-0 = <&pinctrl_gem0_default>;
72 ethernet_phy: ethernet-phy@7 {
78 pinctrl-names = "default";
79 pinctrl-0 = <&pinctrl_gpio0_default>;
84 clock-frequency = <400000>;
85 pinctrl-names = "default";
86 pinctrl-0 = <&pinctrl_i2c0_default>;
89 compatible = "nxp,pca9548";
98 si570: clock-generator@5d {
100 compatible = "silabs,si570";
101 temperature-stability = <50>;
103 factory-fout = <156250000>;
104 clock-frequency = <148500000>;
109 #address-cells = <1>;
113 compatible = "at,24c08";
119 #address-cells = <1>;
123 compatible = "ti,tca6416";
131 #address-cells = <1>;
135 compatible = "nxp,pcf8563";
141 #address-cells = <1>;
145 compatible = "ti,ucd9248";
149 compatible = "ti,ucd9248";
153 compatible = "ti,ucd9248";
161 pinctrl_can0_default: can0-default {
164 groups = "can0_9_grp";
168 groups = "can0_9_grp";
184 pinctrl_gem0_default: gem0-default {
186 function = "ethernet0";
187 groups = "ethernet0_0_grp";
191 groups = "ethernet0_0_grp";
197 pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27";
203 pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21";
210 groups = "mdio0_0_grp";
214 groups = "mdio0_0_grp";
221 pinctrl_gpio0_default: gpio0-default {
224 groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp",
225 "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp",
226 "gpio0_13_grp", "gpio0_14_grp";
230 groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp",
231 "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp",
232 "gpio0_13_grp", "gpio0_14_grp";
238 pins = "MIO9", "MIO10", "MIO11", "MIO12", "MIO13", "MIO14";
243 pins = "MIO7", "MIO8";
248 pinctrl_i2c0_default: i2c0-default {
250 groups = "i2c0_10_grp";
255 groups = "i2c0_10_grp";
262 pinctrl_sdhci0_default: sdhci0-default {
264 groups = "sdio0_2_grp";
269 groups = "sdio0_2_grp";
276 groups = "gpio0_0_grp";
277 function = "sdio0_cd";
281 groups = "gpio0_0_grp";
289 groups = "gpio0_15_grp";
290 function = "sdio0_wp";
294 groups = "gpio0_15_grp";
302 pinctrl_uart1_default: uart1-default {
304 groups = "uart1_10_grp";
309 groups = "uart1_10_grp";
325 pinctrl_usb0_default: usb0-default {
327 groups = "usb0_0_grp";
332 groups = "usb0_0_grp";
338 pins = "MIO29", "MIO31", "MIO36";
343 pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34",
344 "MIO35", "MIO37", "MIO38", "MIO39";
352 pinctrl-names = "default";
353 pinctrl-0 = <&pinctrl_sdhci0_default>;
358 pinctrl-names = "default";
359 pinctrl-0 = <&pinctrl_uart1_default>;
365 usb-phy = <&usb_phy0>;
366 pinctrl-names = "default";
367 pinctrl-0 = <&pinctrl_usb0_default>;