2 * Xilinx ZC702 board DTS
4 * Copyright (C) 2011 - 2015 Xilinx
5 * Copyright (C) 2012 National Instruments Corp.
7 * SPDX-License-Identifier: GPL-2.0+
10 #include "zynq-7000.dtsi"
13 model = "Zynq ZC702 Development Board";
14 compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000";
25 device_type = "memory";
26 reg = <0x0 0x40000000>;
30 bootargs = "earlyprintk";
31 stdout-path = "serial0:115200n8";
35 compatible = "gpio-keys";
41 gpios = <&gpio0 12 0>;
42 linux,code = <108>; /* down */
48 gpios = <&gpio0 14 0>;
49 linux,code = <103>; /* up */
56 compatible = "gpio-leds";
60 gpios = <&gpio0 10 0>;
61 linux,default-trigger = "heartbeat";
66 compatible = "usb-nop-xceiv";
73 compatible = "mmio-sram";
74 reg = <0xfffc0000 0x10000>;
80 pinctrl-names = "default";
81 pinctrl-0 = <&pinctrl_can0_default>;
85 ps-clk-frequency = <33333333>;
90 phy-mode = "rgmii-id";
91 phy-handle = <ðernet_phy>;
92 pinctrl-names = "default";
93 pinctrl-0 = <&pinctrl_gem0_default>;
95 ethernet_phy: ethernet-phy@7 {
101 pinctrl-names = "default";
102 pinctrl-0 = <&pinctrl_gpio0_default>;
107 clock-frequency = <400000>;
108 pinctrl-names = "default";
109 pinctrl-0 = <&pinctrl_i2c0_default>;
112 compatible = "nxp,pca9548";
113 #address-cells = <1>;
118 #address-cells = <1>;
121 si570: clock-generator@5d {
123 compatible = "silabs,si570";
124 temperature-stability = <50>;
126 factory-fout = <156250000>;
127 clock-frequency = <148500000>;
132 #address-cells = <1>;
136 compatible = "at,24c08";
142 #address-cells = <1>;
146 compatible = "ti,tca6416";
154 #address-cells = <1>;
158 compatible = "nxp,pcf8563";
164 #address-cells = <1>;
168 compatible = "ti,ucd9248";
172 compatible = "ti,ucd9248";
176 compatible = "ti,ucd9248";
184 pinctrl_can0_default: can0-default {
187 groups = "can0_9_grp";
191 groups = "can0_9_grp";
207 pinctrl_gem0_default: gem0-default {
209 function = "ethernet0";
210 groups = "ethernet0_0_grp";
214 groups = "ethernet0_0_grp";
220 pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27";
226 pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21";
233 groups = "mdio0_0_grp";
237 groups = "mdio0_0_grp";
244 pinctrl_gpio0_default: gpio0-default {
247 groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp",
248 "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp",
249 "gpio0_13_grp", "gpio0_14_grp";
253 groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp",
254 "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp",
255 "gpio0_13_grp", "gpio0_14_grp";
261 pins = "MIO9", "MIO10", "MIO11", "MIO12", "MIO13", "MIO14";
266 pins = "MIO7", "MIO8";
271 pinctrl_i2c0_default: i2c0-default {
273 groups = "i2c0_10_grp";
278 groups = "i2c0_10_grp";
285 pinctrl_sdhci0_default: sdhci0-default {
287 groups = "sdio0_2_grp";
292 groups = "sdio0_2_grp";
299 groups = "gpio0_0_grp";
300 function = "sdio0_cd";
304 groups = "gpio0_0_grp";
312 groups = "gpio0_15_grp";
313 function = "sdio0_wp";
317 groups = "gpio0_15_grp";
325 pinctrl_uart1_default: uart1-default {
327 groups = "uart1_10_grp";
332 groups = "uart1_10_grp";
348 pinctrl_usb0_default: usb0-default {
350 groups = "usb0_0_grp";
355 groups = "usb0_0_grp";
361 pins = "MIO29", "MIO31", "MIO36";
366 pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34",
367 "MIO35", "MIO37", "MIO38", "MIO39";
376 pinctrl-names = "default";
377 pinctrl-0 = <&pinctrl_sdhci0_default>;
383 pinctrl-names = "default";
384 pinctrl-0 = <&pinctrl_uart1_default>;
395 usb-phy = <&usb_phy0>;
396 pinctrl-names = "default";
397 pinctrl-0 = <&pinctrl_usb0_default>;