2 * Xilinx ZC702 board DTS
4 * Copyright (C) 2011 - 2015 Xilinx
5 * Copyright (C) 2012 National Instruments Corp.
7 * SPDX-License-Identifier: GPL-2.0+
10 #include "zynq-7000.dtsi"
13 model = "Zynq ZC702 Development Board";
14 compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000";
23 device_type = "memory";
24 reg = <0x0 0x40000000>;
28 bootargs = "earlyprintk";
29 stdout-path = "serial0:115200n8";
33 compatible = "gpio-keys";
39 gpios = <&gpio0 12 0>;
40 linux,code = <108>; /* down */
46 gpios = <&gpio0 14 0>;
47 linux,code = <103>; /* up */
54 compatible = "gpio-leds";
58 gpios = <&gpio0 10 0>;
59 linux,default-trigger = "heartbeat";
64 compatible = "usb-nop-xceiv";
71 compatible = "mmio-sram";
72 reg = <0xfffc0000 0x10000>;
78 pinctrl-names = "default";
79 pinctrl-0 = <&pinctrl_can0_default>;
83 ps-clk-frequency = <33333333>;
88 phy-mode = "rgmii-id";
89 phy-handle = <ðernet_phy>;
90 pinctrl-names = "default";
91 pinctrl-0 = <&pinctrl_gem0_default>;
93 ethernet_phy: ethernet-phy@7 {
99 pinctrl-names = "default";
100 pinctrl-0 = <&pinctrl_gpio0_default>;
105 clock-frequency = <400000>;
106 pinctrl-names = "default";
107 pinctrl-0 = <&pinctrl_i2c0_default>;
110 compatible = "nxp,pca9548";
111 #address-cells = <1>;
116 #address-cells = <1>;
119 si570: clock-generator@5d {
121 compatible = "silabs,si570";
122 temperature-stability = <50>;
124 factory-fout = <156250000>;
125 clock-frequency = <148500000>;
130 #address-cells = <1>;
134 compatible = "at,24c08";
140 #address-cells = <1>;
144 compatible = "ti,tca6416";
152 #address-cells = <1>;
156 compatible = "nxp,pcf8563";
162 #address-cells = <1>;
166 compatible = "ti,ucd9248";
170 compatible = "ti,ucd9248";
174 compatible = "ti,ucd9248";
182 pinctrl_can0_default: can0-default {
185 groups = "can0_9_grp";
189 groups = "can0_9_grp";
205 pinctrl_gem0_default: gem0-default {
207 function = "ethernet0";
208 groups = "ethernet0_0_grp";
212 groups = "ethernet0_0_grp";
218 pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27";
224 pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21";
231 groups = "mdio0_0_grp";
235 groups = "mdio0_0_grp";
242 pinctrl_gpio0_default: gpio0-default {
245 groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp",
246 "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp",
247 "gpio0_13_grp", "gpio0_14_grp";
251 groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp",
252 "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp",
253 "gpio0_13_grp", "gpio0_14_grp";
259 pins = "MIO9", "MIO10", "MIO11", "MIO12", "MIO13", "MIO14";
264 pins = "MIO7", "MIO8";
269 pinctrl_i2c0_default: i2c0-default {
271 groups = "i2c0_10_grp";
276 groups = "i2c0_10_grp";
283 pinctrl_sdhci0_default: sdhci0-default {
285 groups = "sdio0_2_grp";
290 groups = "sdio0_2_grp";
297 groups = "gpio0_0_grp";
298 function = "sdio0_cd";
302 groups = "gpio0_0_grp";
310 groups = "gpio0_15_grp";
311 function = "sdio0_wp";
315 groups = "gpio0_15_grp";
323 pinctrl_uart1_default: uart1-default {
325 groups = "uart1_10_grp";
330 groups = "uart1_10_grp";
346 pinctrl_usb0_default: usb0-default {
348 groups = "usb0_0_grp";
353 groups = "usb0_0_grp";
359 pins = "MIO29", "MIO31", "MIO36";
364 pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34",
365 "MIO35", "MIO37", "MIO38", "MIO39";
373 pinctrl-names = "default";
374 pinctrl-0 = <&pinctrl_sdhci0_default>;
379 pinctrl-names = "default";
380 pinctrl-0 = <&pinctrl_uart1_default>;
386 usb-phy = <&usb_phy0>;
387 pinctrl-names = "default";
388 pinctrl-0 = <&pinctrl_usb0_default>;