git.sur5r.net Git - u-boot/blob - arch/arm/dts/zynq-zc702.dts

   1 /*
   2  * Xilinx ZC702 board DTS
   3  *
   4  *  Copyright (C) 2011 - 2015 Xilinx
   5  *  Copyright (C) 2012 National Instruments Corp.
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9 /dts-v1/;
  10 #include "zynq-7000.dtsi"
  11
  12 / {
  13         model = "Zynq ZC702 Development Board";
  14         compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000";
  15
  16         aliases {
  17                 ethernet0 = &gem0;
  18                 i2c0 = &i2c0;
  19                 serial0 = &uart1;
  20                 spi0 = &qspi;
  21                 mmc0 = &sdhci0;
  22         };
  23
  24         memory {
  25                 device_type = "memory";
  26                 reg = <0x0 0x40000000>;
  27         };
  28
  29         chosen {
  30                 bootargs = "earlyprintk";
  31                 stdout-path = "serial0:115200n8";
  32         };
  33
  34         gpio-keys {
  35                 compatible = "gpio-keys";
  36                 #address-cells = <1>;
  37                 #size-cells = <0>;
  38                 autorepeat;
  39                 sw14 {
  40                         label = "sw14";
  41                         gpios = <&gpio0 12 0>;
  42                         linux,code = <108>; /* down */
  43                         gpio-key,wakeup;
  44                         autorepeat;
  45                 };
  46                 sw13 {
  47                         label = "sw13";
  48                         gpios = <&gpio0 14 0>;
  49                         linux,code = <103>; /* up */
  50                         gpio-key,wakeup;
  51                         autorepeat;
  52                 };
  53         };
  54
  55         leds {
  56                 compatible = "gpio-leds";
  57
  58                 ds23 {
  59                         label = "ds23";
  60                         gpios = <&gpio0 10 0>;
  61                         linux,default-trigger = "heartbeat";
  62                 };
  63         };
  64
  65         usb_phy0: phy0 {
  66                 compatible = "usb-nop-xceiv";
  67                 #phy-cells = <0>;
  68         };
  69 };
  70
  71 &amba {
  72         ocm: sram@fffc0000 {
  73                 compatible = "mmio-sram";
  74                 reg = <0xfffc0000 0x10000>;
  75         };
  76 };
  77
  78 &can0 {
  79         status = "okay";
  80         pinctrl-names = "default";
  81         pinctrl-0 = <&pinctrl_can0_default>;
  82 };
  83
  84 &clkc {
  85         ps-clk-frequency = <33333333>;
  86 };
  87
  88 &gem0 {
  89         status = "okay";
  90         phy-mode = "rgmii-id";
  91         phy-handle = <&ethernet_phy>;
  92         pinctrl-names = "default";
  93         pinctrl-0 = <&pinctrl_gem0_default>;
  94
  95         ethernet_phy: ethernet-phy@7 {
  96                 reg = <7>;
  97         };
  98 };
  99
 100 &gpio0 {
 101         pinctrl-names = "default";
 102         pinctrl-0 = <&pinctrl_gpio0_default>;
 103 };
 104
 105 &i2c0 {
 106         status = "okay";
 107         clock-frequency = <400000>;
 108         pinctrl-names = "default";
 109         pinctrl-0 = <&pinctrl_i2c0_default>;
 110
 111         i2cswitch@74 {
 112                 compatible = "nxp,pca9548";
 113                 #address-cells = <1>;
 114                 #size-cells = <0>;
 115                 reg = <0x74>;
 116
 117                 i2c@0 {
 118                         #address-cells = <1>;
 119                         #size-cells = <0>;
 120                         reg = <0>;
 121                         si570: clock-generator@5d {
 122                                 #clock-cells = <0>;
 123                                 compatible = "silabs,si570";
 124                                 temperature-stability = <50>;
 125                                 reg = <0x5d>;
 126                                 factory-fout = <156250000>;
 127                                 clock-frequency = <148500000>;
 128                         };
 129                 };
 130
 131                 i2c@2 {
 132                         #address-cells = <1>;
 133                         #size-cells = <0>;
 134                         reg = <2>;
 135                         eeprom@54 {
 136                                 compatible = "at,24c08";
 137                                 reg = <0x54>;
 138                         };
 139                 };
 140
 141                 i2c@3 {
 142                         #address-cells = <1>;
 143                         #size-cells = <0>;
 144                         reg = <3>;
 145                         gpio@21 {
 146                                 compatible = "ti,tca6416";
 147                                 reg = <0x21>;
 148                                 gpio-controller;
 149                                 #gpio-cells = <2>;
 150                         };
 151                 };
 152
 153                 i2c@4 {
 154                         #address-cells = <1>;
 155                         #size-cells = <0>;
 156                         reg = <4>;
 157                         rtc@51 {
 158                                 compatible = "nxp,pcf8563";
 159                                 reg = <0x51>;
 160                         };
 161                 };
 162
 163                 i2c@7 {
 164                         #address-cells = <1>;
 165                         #size-cells = <0>;
 166                         reg = <7>;
 167                         hwmon@52 {
 168                                 compatible = "ti,ucd9248";
 169                                 reg = <52>;
 170                         };
 171                         hwmon@53 {
 172                                 compatible = "ti,ucd9248";
 173                                 reg = <53>;
 174                         };
 175                         hwmon@54 {
 176                                 compatible = "ti,ucd9248";
 177                                 reg = <54>;
 178                         };
 179                 };
 180         };
 181 };
 182
 183 &pinctrl0 {
 184         pinctrl_can0_default: can0-default {
 185                 mux {
 186                         function = "can0";
 187                         groups = "can0_9_grp";
 188                 };
 189
 190                 conf {
 191                         groups = "can0_9_grp";
 192                         slew-rate = <0>;
 193                         io-standard = <1>;
 194                 };
 195
 196                 conf-rx {
 197                         pins = "MIO46";
 198                         bias-high-impedance;
 199                 };
 200
 201                 conf-tx {
 202                         pins = "MIO47";
 203                         bias-disable;
 204                 };
 205         };
 206
 207         pinctrl_gem0_default: gem0-default {
 208                 mux {
 209                         function = "ethernet0";
 210                         groups = "ethernet0_0_grp";
 211                 };
 212
 213                 conf {
 214                         groups = "ethernet0_0_grp";
 215                         slew-rate = <0>;
 216                         io-standard = <4>;
 217                 };
 218
 219                 conf-rx {
 220                         pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27";
 221                         bias-high-impedance;
 222                         low-power-disable;
 223                 };
 224
 225                 conf-tx {
 226                         pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21";
 227                         bias-disable;
 228                         low-power-enable;
 229                 };
 230
 231                 mux-mdio {
 232                         function = "mdio0";
 233                         groups = "mdio0_0_grp";
 234                 };
 235
 236                 conf-mdio {
 237                         groups = "mdio0_0_grp";
 238                         slew-rate = <0>;
 239                         io-standard = <1>;
 240                         bias-disable;
 241                 };
 242         };
 243
 244         pinctrl_gpio0_default: gpio0-default {
 245                 mux {
 246                         function = "gpio0";
 247                         groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp",
 248                                  "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp",
 249                                  "gpio0_13_grp", "gpio0_14_grp";
 250                 };
 251
 252                 conf {
 253                         groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp",
 254                                  "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp",
 255                                  "gpio0_13_grp", "gpio0_14_grp";
 256                         slew-rate = <0>;
 257                         io-standard = <1>;
 258                 };
 259
 260                 conf-pull-up {
 261                         pins = "MIO9", "MIO10", "MIO11", "MIO12", "MIO13", "MIO14";
 262                         bias-pull-up;
 263                 };
 264
 265                 conf-pull-none {
 266                         pins = "MIO7", "MIO8";
 267                         bias-disable;
 268                 };
 269         };
 270
 271         pinctrl_i2c0_default: i2c0-default {
 272                 mux {
 273                         groups = "i2c0_10_grp";
 274                         function = "i2c0";
 275                 };
 276
 277                 conf {
 278                         groups = "i2c0_10_grp";
 279                         bias-pull-up;
 280                         slew-rate = <0>;
 281                         io-standard = <1>;
 282                 };
 283         };
 284
 285         pinctrl_sdhci0_default: sdhci0-default {
 286                 mux {
 287                         groups = "sdio0_2_grp";
 288                         function = "sdio0";
 289                 };
 290
 291                 conf {
 292                         groups = "sdio0_2_grp";
 293                         slew-rate = <0>;
 294                         io-standard = <1>;
 295                         bias-disable;
 296                 };
 297
 298                 mux-cd {
 299                         groups = "gpio0_0_grp";
 300                         function = "sdio0_cd";
 301                 };
 302
 303                 conf-cd {
 304                         groups = "gpio0_0_grp";
 305                         bias-high-impedance;
 306                         bias-pull-up;
 307                         slew-rate = <0>;
 308                         io-standard = <1>;
 309                 };
 310
 311                 mux-wp {
 312                         groups = "gpio0_15_grp";
 313                         function = "sdio0_wp";
 314                 };
 315
 316                 conf-wp {
 317                         groups = "gpio0_15_grp";
 318                         bias-high-impedance;
 319                         bias-pull-up;
 320                         slew-rate = <0>;
 321                         io-standard = <1>;
 322                 };
 323         };
 324
 325         pinctrl_uart1_default: uart1-default {
 326                 mux {
 327                         groups = "uart1_10_grp";
 328                         function = "uart1";
 329                 };
 330
 331                 conf {
 332                         groups = "uart1_10_grp";
 333                         slew-rate = <0>;
 334                         io-standard = <1>;
 335                 };
 336
 337                 conf-rx {
 338                         pins = "MIO49";
 339                         bias-high-impedance;
 340                 };
 341
 342                 conf-tx {
 343                         pins = "MIO48";
 344                         bias-disable;
 345                 };
 346         };
 347
 348         pinctrl_usb0_default: usb0-default {
 349                 mux {
 350                         groups = "usb0_0_grp";
 351                         function = "usb0";
 352                 };
 353
 354                 conf {
 355                         groups = "usb0_0_grp";
 356                         slew-rate = <0>;
 357                         io-standard = <1>;
 358                 };
 359
 360                 conf-rx {
 361                         pins = "MIO29", "MIO31", "MIO36";
 362                         bias-high-impedance;
 363                 };
 364
 365                 conf-tx {
 366                         pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34",
 367                                "MIO35", "MIO37", "MIO38", "MIO39";
 368                         bias-disable;
 369                 };
 370         };
 371 };
 372
 373 &sdhci0 {
 374         u-boot,dm-pre-reloc;
 375         status = "okay";
 376         pinctrl-names = "default";
 377         pinctrl-0 = <&pinctrl_sdhci0_default>;
 378 };
 379
 380 &uart1 {
 381         u-boot,dm-pre-reloc;
 382         status = "okay";
 383         pinctrl-names = "default";
 384         pinctrl-0 = <&pinctrl_uart1_default>;
 385 };
 386
 387 &qspi {
 388         u-boot,dm-pre-reloc;
 389         status = "okay";
 390 };
 391
 392 &usb0 {
 393         status = "okay";
 394         dr_mode = "host";
 395         usb-phy = <&usb_phy0>;
 396         pinctrl-names = "default";
 397         pinctrl-0 = <&pinctrl_usb0_default>;
 398 };