2 * Xilinx ZC706 board DTS
4 * Copyright (C) 2011 - 2015 Xilinx
5 * Copyright (C) 2012 National Instruments Corp.
7 * SPDX-License-Identifier: GPL-2.0+
10 #include "zynq-7000.dtsi"
13 model = "Zynq ZC706 Development Board";
14 compatible = "xlnx,zynq-zc706", "xlnx,zynq-7000";
23 device_type = "memory";
24 reg = <0x0 0x40000000>;
28 bootargs = "earlyprintk";
29 stdout-path = "serial0:115200n8";
33 compatible = "usb-nop-xceiv";
39 ps-clk-frequency = <33333333>;
44 phy-mode = "rgmii-id";
45 phy-handle = <ðernet_phy>;
46 pinctrl-names = "default";
47 pinctrl-0 = <&pinctrl_gem0_default>;
49 ethernet_phy: ethernet-phy@7 {
55 pinctrl-names = "default";
56 pinctrl-0 = <&pinctrl_gpio0_default>;
61 clock-frequency = <400000>;
62 pinctrl-names = "default";
63 pinctrl-0 = <&pinctrl_i2c0_default>;
66 compatible = "nxp,pca9548";
75 si570: clock-generator@5d {
77 compatible = "silabs,si570";
78 temperature-stability = <50>;
80 factory-fout = <156250000>;
81 clock-frequency = <148500000>;
90 compatible = "at,24c08";
100 compatible = "ti,tca6416";
108 #address-cells = <1>;
112 compatible = "nxp,pcf8563";
118 #address-cells = <1>;
122 compatible = "ti,ucd90120";
130 pinctrl_gem0_default: gem0-default {
132 function = "ethernet0";
133 groups = "ethernet0_0_grp";
137 groups = "ethernet0_0_grp";
143 pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27";
149 pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21";
156 groups = "mdio0_0_grp";
160 groups = "mdio0_0_grp";
167 pinctrl_gpio0_default: gpio0-default {
170 groups = "gpio0_7_grp", "gpio0_46_grp", "gpio0_47_grp";
174 groups = "gpio0_7_grp", "gpio0_46_grp", "gpio0_47_grp";
180 pins = "MIO46", "MIO47";
190 pinctrl_i2c0_default: i2c0-default {
192 groups = "i2c0_10_grp";
197 groups = "i2c0_10_grp";
204 pinctrl_sdhci0_default: sdhci0-default {
206 groups = "sdio0_2_grp";
211 groups = "sdio0_2_grp";
218 groups = "gpio0_14_grp";
219 function = "sdio0_cd";
223 groups = "gpio0_14_grp";
231 groups = "gpio0_15_grp";
232 function = "sdio0_wp";
236 groups = "gpio0_15_grp";
244 pinctrl_uart1_default: uart1-default {
246 groups = "uart1_10_grp";
251 groups = "uart1_10_grp";
267 pinctrl_usb0_default: usb0-default {
269 groups = "usb0_0_grp";
274 groups = "usb0_0_grp";
280 pins = "MIO29", "MIO31", "MIO36";
285 pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34",
286 "MIO35", "MIO37", "MIO38", "MIO39";
294 pinctrl-names = "default";
295 pinctrl-0 = <&pinctrl_sdhci0_default>;
300 pinctrl-names = "default";
301 pinctrl-0 = <&pinctrl_uart1_default>;
307 usb-phy = <&usb_phy0>;
308 pinctrl-names = "default";
309 pinctrl-0 = <&pinctrl_usb0_default>;