2 * Xilinx ZC706 board DTS
4 * Copyright (C) 2011 - 2015 Xilinx
5 * Copyright (C) 2012 National Instruments Corp.
7 * SPDX-License-Identifier: GPL-2.0+
10 #include "zynq-7000.dtsi"
13 model = "Zynq ZC706 Development Board";
14 compatible = "xlnx,zynq-zc706", "xlnx,zynq-7000";
24 device_type = "memory";
25 reg = <0x0 0x40000000>;
29 bootargs = "earlyprintk";
30 stdout-path = "serial0:115200n8";
34 compatible = "usb-nop-xceiv";
40 ps-clk-frequency = <33333333>;
45 phy-mode = "rgmii-id";
46 phy-handle = <ðernet_phy>;
47 pinctrl-names = "default";
48 pinctrl-0 = <&pinctrl_gem0_default>;
50 ethernet_phy: ethernet-phy@7 {
56 pinctrl-names = "default";
57 pinctrl-0 = <&pinctrl_gpio0_default>;
62 clock-frequency = <400000>;
63 pinctrl-names = "default";
64 pinctrl-0 = <&pinctrl_i2c0_default>;
67 compatible = "nxp,pca9548";
76 si570: clock-generator@5d {
78 compatible = "silabs,si570";
79 temperature-stability = <50>;
81 factory-fout = <156250000>;
82 clock-frequency = <148500000>;
91 compatible = "at,24c08";
101 compatible = "ti,tca6416";
109 #address-cells = <1>;
113 compatible = "nxp,pcf8563";
119 #address-cells = <1>;
123 compatible = "ti,ucd90120";
131 pinctrl_gem0_default: gem0-default {
133 function = "ethernet0";
134 groups = "ethernet0_0_grp";
138 groups = "ethernet0_0_grp";
144 pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27";
150 pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21";
157 groups = "mdio0_0_grp";
161 groups = "mdio0_0_grp";
168 pinctrl_gpio0_default: gpio0-default {
171 groups = "gpio0_7_grp", "gpio0_46_grp", "gpio0_47_grp";
175 groups = "gpio0_7_grp", "gpio0_46_grp", "gpio0_47_grp";
181 pins = "MIO46", "MIO47";
191 pinctrl_i2c0_default: i2c0-default {
193 groups = "i2c0_10_grp";
198 groups = "i2c0_10_grp";
205 pinctrl_sdhci0_default: sdhci0-default {
207 groups = "sdio0_2_grp";
212 groups = "sdio0_2_grp";
219 groups = "gpio0_14_grp";
220 function = "sdio0_cd";
224 groups = "gpio0_14_grp";
232 groups = "gpio0_15_grp";
233 function = "sdio0_wp";
237 groups = "gpio0_15_grp";
245 pinctrl_uart1_default: uart1-default {
247 groups = "uart1_10_grp";
252 groups = "uart1_10_grp";
268 pinctrl_usb0_default: usb0-default {
270 groups = "usb0_0_grp";
275 groups = "usb0_0_grp";
281 pins = "MIO29", "MIO31", "MIO36";
286 pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34",
287 "MIO35", "MIO37", "MIO38", "MIO39";
295 pinctrl-names = "default";
296 pinctrl-0 = <&pinctrl_sdhci0_default>;
301 pinctrl-names = "default";
302 pinctrl-0 = <&pinctrl_uart1_default>;
312 usb-phy = <&usb_phy0>;
313 pinctrl-names = "default";
314 pinctrl-0 = <&pinctrl_usb0_default>;