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[u-boot] / arch / arm / dts / zynqmp-clk.dtsi
1 /*
2  * Clock specification for Xilinx ZynqMP
3  *
4  * (C) Copyright 2015, Xilinx, Inc.
5  *
6  * Michal Simek <michal.simek@xilinx.com>
7  *
8  * SPDX-License-Identifier:     GPL-2.0+
9  */
10
11 &amba {
12         clk100: clk100 {
13                 compatible = "fixed-clock";
14                 #clock-cells = <0>;
15                 clock-frequency = <100000000>;
16         };
17
18         clk125: clk125 {
19                 compatible = "fixed-clock";
20                 #clock-cells = <0>;
21                 clock-frequency = <125000000>;
22         };
23
24         clk200: clk200 {
25                 compatible = "fixed-clock";
26                 #clock-cells = <0>;
27                 clock-frequency = <200000000>;
28         };
29
30         clk250: clk250 {
31                 compatible = "fixed-clock";
32                 #clock-cells = <0>;
33                 clock-frequency = <250000000>;
34         };
35
36         clk300: clk300 {
37                 compatible = "fixed-clock";
38                 #clock-cells = <0>;
39                 clock-frequency = <300000000>;
40         };
41
42         clk600: clk600 {
43                 compatible = "fixed-clock";
44                 #clock-cells = <0>;
45                 clock-frequency = <600000000>;
46         };
47
48         dp_aclk: clock0 {
49                 compatible = "fixed-clock";
50                 #clock-cells = <0>;
51                 clock-frequency = <100000000>;
52                 clock-accuracy = <100>;
53         };
54
55         dp_aud_clk: clock1 {
56                 compatible = "fixed-clock";
57                 #clock-cells = <0>;
58                 clock-frequency = <24576000>;
59                 clock-accuracy = <100>;
60         };
61
62         dpdma_clk: dpdma_clk {
63                 compatible = "fixed-clock";
64                 #clock-cells = <0x0>;
65                 clock-frequency = <533000000>;
66         };
67
68         drm_clock: drm_clock {
69                 compatible = "fixed-clock";
70                 #clock-cells = <0x0>;
71                 clock-frequency = <262750000>;
72                 clock-accuracy = <0x64>;
73         };
74 };
75
76 &can0 {
77         clocks = <&clk100 &clk100>;
78 };
79
80 &can1 {
81         clocks = <&clk100 &clk100>;
82 };
83
84 &fpd_dma_chan1 {
85         clocks = <&clk600>, <&clk100>;
86 };
87
88 &fpd_dma_chan2 {
89         clocks = <&clk600>, <&clk100>;
90 };
91
92 &fpd_dma_chan3 {
93         clocks = <&clk600>, <&clk100>;
94 };
95
96 &fpd_dma_chan4 {
97         clocks = <&clk600>, <&clk100>;
98 };
99
100 &fpd_dma_chan5 {
101         clocks = <&clk600>, <&clk100>;
102 };
103
104 &fpd_dma_chan6 {
105         clocks = <&clk600>, <&clk100>;
106 };
107
108 &fpd_dma_chan7 {
109         clocks = <&clk600>, <&clk100>;
110 };
111
112 &fpd_dma_chan8 {
113         clocks = <&clk600>, <&clk100>;
114 };
115
116 &nand0 {
117         clocks = <&clk100 &clk100>;
118 };
119
120 &gem0 {
121         clocks = <&clk125>, <&clk125>, <&clk125>;
122 };
123
124 &gem1 {
125         clocks = <&clk125>, <&clk125>, <&clk125>;
126 };
127
128 &gem2 {
129         clocks = <&clk125>, <&clk125>, <&clk125>;
130 };
131
132 &gem3 {
133         clocks = <&clk125>, <&clk125>, <&clk125>;
134 };
135
136 &gpio {
137         clocks = <&clk100>;
138 };
139
140 &i2c0 {
141         clocks = <&clk100>;
142 };
143
144 &i2c1 {
145         clocks = <&clk100>;
146 };
147
148 &qspi {
149         clocks = <&clk300 &clk300>;
150 };
151
152 &sata {
153         clocks = <&clk250>;
154 };
155
156 &sdhci0 {
157         clocks = <&clk200 &clk200>;
158 };
159
160 &sdhci1 {
161         clocks = <&clk200 &clk200>;
162 };
163
164 &spi0 {
165         clocks = <&clk200 &clk200>;
166 };
167
168 &spi1 {
169         clocks = <&clk200 &clk200>;
170 };
171
172 &uart0 {
173         clocks = <&clk100 &clk100>;
174 };
175
176 &uart1 {
177         clocks = <&clk100 &clk100>;
178 };
179
180 &usb0 {
181         clocks = <&clk250>, <&clk250>;
182 };
183
184 &usb1 {
185         clocks = <&clk250>, <&clk250>;
186 };
187
188 &xilinx_drm {
189         clocks = <&drm_clock>;
190 };
191
192 &xlnx_dp {
193         clocks = <&dp_aclk>, <&dp_aud_clk>;
194 };
195
196 &xlnx_dpdma {
197         clocks = <&dpdma_clk>;
198 };
199
200 &xlnx_dp_snd_codec0 {
201         clocks = <&dp_aud_clk>;
202 };