2 * clock specification for Xilinx ZynqMP ep108 development board
4 * (C) Copyright 2015, Xilinx, Inc.
6 * Michal Simek <michal.simek@xilinx.com>
8 * SPDX-License-Identifier: GPL-2.0+
13 compatible = "fixed-clock";
15 clock-frequency = <25000000>;
20 compatible = "fixed-clock";
22 clock-frequency = <111111111>;
26 compatible = "fixed-clock";
28 clock-frequency = <75000000>;
32 compatible = "fixed-clock";
34 clock-frequency = <50000000>;
35 clock-accuracy = <100>;
39 compatible = "fixed-clock";
41 clock-frequency = <22579200>;
42 clock-accuracy = <100>;
47 clocks = <&misc_clk &misc_clk>;
51 clocks = <&misc_clk>, <&misc_clk>, <&misc_clk>;
67 clocks = <&misc_clk &misc_clk>;
71 clocks = <&misc_clk &misc_clk>;
79 clocks = <&misc_clk>, <&misc_clk>;
83 clocks = <&misc_clk>, <&misc_clk>;
87 clocks = <&misc_clk &misc_clk>;
91 clocks = <&misc_clk &misc_clk>;
95 clocks = <&misc_clk &misc_clk>;
99 clocks = <&misc_clk>, <&misc_clk>;
103 clocks = <&misc_clk>, <&misc_clk>;
111 clocks = <&misc_clk>;
115 clocks = <&dp_aclk>, <&dp_aud_clk>;
118 &xlnx_dp_snd_codec0 {
119 clocks = <&dp_aud_clk>;
123 clocks = <&misc_clk>;