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[u-boot] / arch / arm / dts / zynqmp-ep108.dts
1 /*
2  * dts file for Xilinx ZynqMP ep108 development board
3  *
4  * (C) Copyright 2014 - 2015, Xilinx, Inc.
5  *
6  * Michal Simek <michal.simek@xilinx.com>
7  *
8  * SPDX-License-Identifier:     GPL-2.0+
9  */
10
11 /dts-v1/;
12
13 #include "zynqmp.dtsi"
14 #include "zynqmp-ep108-clk.dtsi"
15
16 / {
17         model = "ZynqMP EP108";
18
19         aliases {
20                 mmc0 = &sdhci0;
21                 mmc1 = &sdhci1;
22                 serial0 = &uart0;
23                 spi0 = &qspi;
24                 spi1 = &spi0;
25                 spi2 = &spi1;
26                 usb0 = &usb0;
27                 usb1 = &usb1;
28         };
29
30         chosen {
31                 stdout-path = "serial0:115200n8";
32         };
33
34         memory {
35                 device_type = "memory";
36                 reg = <0x0 0x0 0x0 0x40000000>;
37         };
38 };
39
40 &can0 {
41         status = "okay";
42 };
43
44 &gem0 {
45         status = "okay";
46         phy-handle = <&phy0>;
47         phy-mode = "rgmii-id";
48         phy0: phy@0 {
49                 reg = <0>;
50                 max-speed = <100>;
51         };
52 };
53
54 &gpio {
55         status = "okay";
56 };
57
58 &i2c0 {
59         status = "okay";
60         clock-frequency = <400000>;
61         eeprom@54 {
62                 compatible = "at,24c64";
63                 reg = <0x54>;
64         };
65 };
66
67 &i2c1 {
68         status = "okay";
69         clock-frequency = <400000>;
70         eeprom@55 {
71                 compatible = "at,24c64";
72                 reg = <0x55>;
73         };
74 };
75
76 &nand0 {
77         status = "okay";
78         arasan,has-mdma;
79         num-cs = <1>;
80
81         partition@0 {   /* for testing purpose */
82                 label = "nand-fsbl-uboot";
83                 reg = <0x0 0x0 0x400000>;
84         };
85         partition@1 {   /* for testing purpose */
86                 label = "nand-linux";
87                 reg = <0x0 0x400000 0x1400000>;
88         };
89         partition@2 {   /* for testing purpose */
90                 label = "nand-device-tree";
91                 reg = <0x0 0x1800000 0x400000>;
92         };
93         partition@3 {   /* for testing purpose */
94                 label = "nand-rootfs";
95                 reg = <0x0 0x1C00000 0x1400000>;
96         };
97         partition@4 {   /* for testing purpose */
98                 label = "nand-bitstream";
99                 reg = <0x0 0x3000000 0x400000>;
100         };
101         partition@5 {   /* for testing purpose */
102                 label = "nand-misc";
103                 reg = <0x0 0x3400000 0xFCC00000>;
104         };
105 };
106
107 &qspi {
108         status = "okay";
109         flash@0 {
110                 compatible = "m25p80";
111                 #address-cells = <1>;
112                 #size-cells = <1>;
113                 reg = <0x0>;
114                 spi-tx-bus-width = <1>;
115                 spi-rx-bus-width = <4>;
116                 spi-max-frequency = <10000000>;
117                 partition@qspi-fsbl-uboot { /* for testing purpose */
118                         label = "qspi-fsbl-uboot";
119                         reg = <0x0 0x100000>;
120                 };
121                 partition@qspi-linux { /* for testing purpose */
122                         label = "qspi-linux";
123                         reg = <0x100000 0x500000>;
124                 };
125                 partition@qspi-device-tree { /* for testing purpose */
126                         label = "qspi-device-tree";
127                         reg = <0x600000 0x20000>;
128                 };
129                 partition@qspi-rootfs { /* for testing purpose */
130                         label = "qspi-rootfs";
131                         reg = <0x620000 0x5E0000>;
132                 };
133         };
134 };
135
136 &sata {
137         status = "okay";
138         ceva,broken-gen2;
139         /* SATA Phy OOB timing settings */
140         ceva,p0-cominit-params = /bits/ 8 <0x0F 0x25 0x18 0x29>;
141         ceva,p0-comwake-params = /bits/ 8 <0x04 0x0B 0x08 0x0F>;
142         ceva,p0-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>;
143         ceva,p0-retry-params = /bits/ 16 <0x0216 0x7F06>;
144         ceva,p1-cominit-params = /bits/ 8 <0x0F 0x25 0x18 0x29>;
145         ceva,p1-comwake-params = /bits/ 8 <0x04 0x0B 0x08 0x0F>;
146         ceva,p1-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>;
147         ceva,p1-retry-params = /bits/ 16 <0x0216 0x7F06>;
148 };
149
150 &sdhci0 {
151         status = "okay";
152         bus-width = <8>;
153 };
154
155 &sdhci1 {
156         status = "okay";
157 };
158
159 &spi0 {
160         status = "okay";
161         num-cs = <1>;
162         spi0_flash0: spi0_flash0@0 {
163                 compatible = "m25p80";
164                 #address-cells = <1>;
165                 #size-cells = <1>;
166                 spi-max-frequency = <50000000>;
167                 reg = <0>;
168
169                 spi0_flash0@00000000 {
170                         label = "spi0_flash0";
171                         reg = <0x0 0x100000>;
172                 };
173         };
174 };
175
176 &spi1 {
177         status = "okay";
178         num-cs = <1>;
179         spi1_flash0: spi1_flash0@0 {
180                 compatible = "m25p80";
181                 #address-cells = <1>;
182                 #size-cells = <1>;
183                 spi-max-frequency = <50000000>;
184                 reg = <0>;
185
186                 spi1_flash0@00000000 {
187                         label = "spi1_flash0";
188                         reg = <0x0 0x100000>;
189                 };
190         };
191 };
192
193 &uart0 {
194         status = "okay";
195 };
196
197 &usb0 {
198         status = "okay";
199 };
200
201 &dwc3_0 {
202         status = "okay";
203         dr_mode = "peripheral";
204         maximum-speed = "high-speed";
205 };
206
207 &usb1 {
208         status = "okay";
209 };
210
211 &dwc3_1 {
212         status = "okay";
213         dr_mode = "host";
214         maximum-speed = "high-speed";
215 };
216
217 &watchdog0 {
218         status = "okay";
219 };
220
221 &xlnx_dp {
222         xlnx,max-pclock-frequency = <200000>;
223 };
224
225 &xlnx_dpdma {
226         xlnx,axi-clock-freq = <200000000>;
227 };