2 * dts file for Xilinx ZynqMP ep108 development board
4 * (C) Copyright 2014 - 2015, Xilinx, Inc.
6 * Michal Simek <michal.simek@xilinx.com>
8 * SPDX-License-Identifier: GPL-2.0+
13 #include "zynqmp.dtsi"
14 #include "zynqmp-ep108-clk.dtsi"
17 model = "ZynqMP EP108";
31 stdout-path = "serial0:115200n8";
35 device_type = "memory";
36 reg = <0x0 0x0 0x0 0x40000000>;
47 phy-mode = "rgmii-id";
60 clock-frequency = <400000>;
62 compatible = "at,24c64";
69 clock-frequency = <400000>;
71 compatible = "at,24c64";
79 compatible = "m25p80";
83 spi-tx-bus-width = <1>;
84 spi-rx-bus-width = <4>;
85 spi-max-frequency = <10000000>;
86 partition@qspi-fsbl-uboot { /* for testing purpose */
87 label = "qspi-fsbl-uboot";
90 partition@qspi-linux { /* for testing purpose */
92 reg = <0x100000 0x500000>;
94 partition@qspi-device-tree { /* for testing purpose */
95 label = "qspi-device-tree";
96 reg = <0x600000 0x20000>;
98 partition@qspi-rootfs { /* for testing purpose */
99 label = "qspi-rootfs";
100 reg = <0x620000 0x5E0000>;
122 spi0_flash0: spi0_flash0@0 {
123 compatible = "m25p80";
124 #address-cells = <1>;
126 spi-max-frequency = <50000000>;
129 spi0_flash0@00000000 {
130 label = "spi0_flash0";
131 reg = <0x0 0x100000>;
139 spi1_flash0: spi1_flash0@0 {
140 compatible = "m25p80";
141 #address-cells = <1>;
143 spi-max-frequency = <50000000>;
146 spi1_flash0@00000000 {
147 label = "spi1_flash0";
148 reg = <0x0 0x100000>;
163 dr_mode = "peripheral";
164 maximum-speed = "high-speed";
174 maximum-speed = "high-speed";
182 xlnx,max-pclock-frequency = <200000>;
186 xlnx,axi-clock-freq = <200000000>;