git.sur5r.net Git - u-boot/blob - arch/arm/dts/zynqmp-ep108.dts

   1 /*
   2  * dts file for Xilinx ZynqMP ep108 development board
   3  *
   4  * (C) Copyright 2014 - 2015, Xilinx, Inc.
   5  *
   6  * Michal Simek <michal.simek@xilinx.com>
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 /dts-v1/;
  12
  13 #include "zynqmp.dtsi"
  14 #include "zynqmp-ep108-clk.dtsi"
  15
  16 / {
  17         model = "ZynqMP EP108";
  18
  19         aliases {
  20                 mmc0 = &sdhci0;
  21                 mmc1 = &sdhci1;
  22                 serial0 = &uart0;
  23                 spi0 = &qspi;
  24                 spi1 = &spi0;
  25                 spi2 = &spi1;
  26                 usb0 = &usb0;
  27                 usb1 = &usb1;
  28         };
  29
  30         chosen {
  31                 stdout-path = "serial0:115200n8";
  32         };
  33
  34         memory@0 {
  35                 device_type = "memory";
  36                 reg = <0x0 0x0 0x0 0x40000000>;
  37         };
  38 };
  39
  40 &can0 {
  41         status = "okay";
  42 };
  43
  44 &can1 {
  45         status = "okay";
  46 };
  47
  48 &gem0 {
  49         status = "okay";
  50         phy-handle = <&phy0>;
  51         phy-mode = "rgmii-id";
  52         phy0: phy@0 {
  53                 reg = <0>;
  54                 max-speed = <100>;
  55         };
  56 };
  57
  58 &gpio {
  59         status = "okay";
  60 };
  61
  62 &i2c0 {
  63         status = "okay";
  64         clock-frequency = <400000>;
  65         eeprom@54 {
  66                 compatible = "at,24c64";
  67                 reg = <0x54>;
  68         };
  69 };
  70
  71 &i2c1 {
  72         status = "okay";
  73         clock-frequency = <400000>;
  74         eeprom@55 {
  75                 compatible = "at,24c64";
  76                 reg = <0x55>;
  77         };
  78 };
  79
  80 &nand0 {
  81         status = "okay";
  82         arasan,has-mdma;
  83         num-cs = <1>;
  84
  85         partition@0 {   /* for testing purpose */
  86                 label = "nand-fsbl-uboot";
  87                 reg = <0x0 0x0 0x400000>;
  88         };
  89         partition@1 {   /* for testing purpose */
  90                 label = "nand-linux";
  91                 reg = <0x0 0x400000 0x1400000>;
  92         };
  93         partition@2 {   /* for testing purpose */
  94                 label = "nand-device-tree";
  95                 reg = <0x0 0x1800000 0x400000>;
  96         };
  97         partition@3 {   /* for testing purpose */
  98                 label = "nand-rootfs";
  99                 reg = <0x0 0x1C00000 0x1400000>;
 100         };
 101         partition@4 {   /* for testing purpose */
 102                 label = "nand-bitstream";
 103                 reg = <0x0 0x3000000 0x400000>;
 104         };
 105         partition@5 {   /* for testing purpose */
 106                 label = "nand-misc";
 107                 reg = <0x0 0x3400000 0xFCC00000>;
 108         };
 109 };
 110
 111 &qspi {
 112         status = "okay";
 113         flash@0 {
 114                 compatible = "m25p80";
 115                 #address-cells = <1>;
 116                 #size-cells = <1>;
 117                 reg = <0x0>;
 118                 spi-tx-bus-width = <1>;
 119                 spi-rx-bus-width = <4>;
 120                 spi-max-frequency = <10000000>;
 121                 partition@qspi-fsbl-uboot { /* for testing purpose */
 122                         label = "qspi-fsbl-uboot";
 123                         reg = <0x0 0x100000>;
 124                 };
 125                 partition@qspi-linux { /* for testing purpose */
 126                         label = "qspi-linux";
 127                         reg = <0x100000 0x500000>;
 128                 };
 129                 partition@qspi-device-tree { /* for testing purpose */
 130                         label = "qspi-device-tree";
 131                         reg = <0x600000 0x20000>;
 132                 };
 133                 partition@qspi-rootfs { /* for testing purpose */
 134                         label = "qspi-rootfs";
 135                         reg = <0x620000 0x5E0000>;
 136                 };
 137         };
 138 };
 139
 140 &sata {
 141         status = "okay";
 142         ceva,broken-gen2;
 143         /* SATA Phy OOB timing settings */
 144         ceva,p0-cominit-params = /bits/ 8 <0x0F 0x25 0x18 0x29>;
 145         ceva,p0-comwake-params = /bits/ 8 <0x04 0x0B 0x08 0x0F>;
 146         ceva,p0-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>;
 147         ceva,p0-retry-params = /bits/ 16 <0x0216 0x7F06>;
 148         ceva,p1-cominit-params = /bits/ 8 <0x0F 0x25 0x18 0x29>;
 149         ceva,p1-comwake-params = /bits/ 8 <0x04 0x0B 0x08 0x0F>;
 150         ceva,p1-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>;
 151         ceva,p1-retry-params = /bits/ 16 <0x0216 0x7F06>;
 152 };
 153
 154 &sdhci0 {
 155         status = "okay";
 156         bus-width = <8>;
 157         xlnx,mio_bank = <2>;
 158 };
 159
 160 &sdhci1 {
 161         status = "okay";
 162         xlnx,mio_bank = <1>;
 163 };
 164
 165 &spi0 {
 166         status = "okay";
 167         num-cs = <1>;
 168         spi0_flash0: spi0_flash0@0 {
 169                 compatible = "m25p80";
 170                 #address-cells = <1>;
 171                 #size-cells = <1>;
 172                 spi-max-frequency = <50000000>;
 173                 reg = <0>;
 174
 175                 spi0_flash0@00000000 {
 176                         label = "spi0_flash0";
 177                         reg = <0x0 0x100000>;
 178                 };
 179         };
 180 };
 181
 182 &spi1 {
 183         status = "okay";
 184         num-cs = <1>;
 185         spi1_flash0: spi1_flash0@0 {
 186                 compatible = "m25p80";
 187                 #address-cells = <1>;
 188                 #size-cells = <1>;
 189                 spi-max-frequency = <50000000>;
 190                 reg = <0>;
 191
 192                 spi1_flash0@00000000 {
 193                         label = "spi1_flash0";
 194                         reg = <0x0 0x100000>;
 195                 };
 196         };
 197 };
 198
 199 &uart0 {
 200         status = "okay";
 201 };
 202
 203 &usb0 {
 204         status = "okay";
 205 };
 206
 207 &dwc3_0 {
 208         status = "okay";
 209         dr_mode = "peripheral";
 210         maximum-speed = "high-speed";
 211 };
 212
 213 &usb1 {
 214         status = "okay";
 215 };
 216
 217 &dwc3_1 {
 218         status = "okay";
 219         dr_mode = "host";
 220         maximum-speed = "high-speed";
 221 };
 222
 223 &watchdog0 {
 224         status = "okay";
 225 };
 226
 227 &xlnx_dp {
 228         xlnx,max-pclock-frequency = <200000>;
 229 };
 230
 231 &xlnx_dpdma {
 232         xlnx,axi-clock-freq = <200000000>;
 233 };