2 * dts file for Xilinx ZynqMP ep108 development board
4 * (C) Copyright 2014 - 2015, Xilinx, Inc.
6 * Michal Simek <michal.simek@xilinx.com>
8 * SPDX-License-Identifier: GPL-2.0+
13 #include "zynqmp.dtsi"
14 #include "zynqmp-ep108-clk.dtsi"
17 model = "ZynqMP EP108";
29 stdout-path = "serial0:115200n8";
33 device_type = "memory";
34 reg = <0x0 0x0 0x40000000>;
45 phy-mode = "rgmii-id";
58 clock-frequency = <400000>;
60 compatible = "at,24c64";
67 clock-frequency = <400000>;
69 compatible = "at,24c64";
77 compatible = "n25q512a11";
81 spi-tx-bus-width = <1>;
82 spi-rx-bus-width = <4>;
83 spi-max-frequency = <10000000>;
84 partition@qspi-fsbl-uboot { /* for testing purpose */
85 label = "qspi-fsbl-uboot";
88 partition@qspi-linux { /* for testing purpose */
90 reg = <0x100000 0x500000>;
92 partition@qspi-device-tree { /* for testing purpose */
93 label = "qspi-device-tree";
94 reg = <0x600000 0x20000>;
96 partition@qspi-rootfs { /* for testing purpose */
97 label = "qspi-rootfs";
98 reg = <0x620000 0x5E0000>;
119 spi0_flash0: spi0_flash0@0 {
120 compatible = "m25p80";
121 #address-cells = <1>;
123 spi-max-frequency = <50000000>;
126 spi0_flash0@00000000 {
127 label = "spi0_flash0";
128 reg = <0x0 0x100000>;
136 spi1_flash0: spi1_flash0@0 {
137 compatible = "m25p80";
138 #address-cells = <1>;
140 spi-max-frequency = <50000000>;
143 spi1_flash0@00000000 {
144 label = "spi1_flash0";
145 reg = <0x0 0x100000>;
156 dr_mode = "peripheral";
157 maximum-speed = "high-speed";
163 maximum-speed = "high-speed";
171 xlnx,max-pclock-frequency = <200000>;
175 xlnx,axi-clock-freq = <200000000>;