git.sur5r.net Git - u-boot/blob - arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts

   1 /*
   2  * dts file for Xilinx ZynqMP zc1751-xm015-dc1
   3  *
   4  * (C) Copyright 2015, Xilinx, Inc.
   5  *
   6  * Michal Simek <michal.simek@xilinx.com>
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 /dts-v1/;
  12
  13 #include "zynqmp.dtsi"
  14 #include "zynqmp-clk-ccf.dtsi"
  15
  16 / {
  17         model = "ZynqMP zc1751-xm015-dc1 RevA";
  18         compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
  19
  20         aliases {
  21                 ethernet0 = &gem3;
  22                 gpio0 = &gpio;
  23                 i2c0 = &i2c1;
  24                 mmc0 = &sdhci0;
  25                 mmc1 = &sdhci1;
  26                 rtc0 = &rtc;
  27                 serial0 = &uart0;
  28                 spi0 = &qspi;
  29                 usb0 = &usb0;
  30         };
  31
  32         chosen {
  33                 bootargs = "earlycon";
  34                 stdout-path = "serial0:115200n8";
  35         };
  36
  37         memory@0 {
  38                 device_type = "memory";
  39                 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
  40         };
  41 };
  42
  43 /* fpd_dma clk 667MHz, lpd_dma 500MHz */
  44 &fpd_dma_chan1 {
  45         status = "okay";
  46 };
  47
  48 &fpd_dma_chan2 {
  49         status = "okay";
  50 };
  51
  52 &fpd_dma_chan3 {
  53         status = "okay";
  54 };
  55
  56 &fpd_dma_chan4 {
  57         status = "okay";
  58 };
  59
  60 &fpd_dma_chan5 {
  61         status = "okay";
  62 };
  63
  64 &fpd_dma_chan6 {
  65         status = "okay";
  66 };
  67
  68 &fpd_dma_chan7 {
  69         status = "okay";
  70 };
  71
  72 &fpd_dma_chan8 {
  73         status = "okay";
  74 };
  75
  76 &gem3 {
  77         status = "okay";
  78         phy-handle = <&phy0>;
  79         phy-mode = "rgmii-id";
  80         phy0: phy@0 {
  81                 reg = <0>;
  82         };
  83 };
  84
  85 &gpio {
  86         status = "okay";
  87 };
  88
  89 &gpu {
  90         status = "okay";
  91 };
  92
  93 &i2c1 {
  94         status = "okay";
  95         clock-frequency = <400000>;
  96         eeprom@55 {
  97                 compatible = "at,24c64"; /* 24AA64 */
  98                 reg = <0x55>;
  99         };
 100 };
 101
 102 &qspi {
 103         status = "okay";
 104         flash@0 {
 105                 compatible = "m25p80"; /* Micron MT25QU512ABB8ESF */
 106                 #address-cells = <1>;
 107                 #size-cells = <1>;
 108                 reg = <0x0>;
 109                 spi-tx-bus-width = <1>;
 110                 spi-rx-bus-width = <4>;
 111                 spi-max-frequency = <108000000>; /* Based on DC1 spec */
 112                 partition@qspi-fsbl-uboot { /* for testing purpose */
 113                         label = "qspi-fsbl-uboot";
 114                         reg = <0x0 0x100000>;
 115                 };
 116                 partition@qspi-linux { /* for testing purpose */
 117                         label = "qspi-linux";
 118                         reg = <0x100000 0x500000>;
 119                 };
 120                 partition@qspi-device-tree { /* for testing purpose */
 121                         label = "qspi-device-tree";
 122                         reg = <0x600000 0x20000>;
 123                 };
 124                 partition@qspi-rootfs { /* for testing purpose */
 125                         label = "qspi-rootfs";
 126                         reg = <0x620000 0x5E0000>;
 127                 };
 128         };
 129 };
 130
 131 &rtc {
 132         status = "okay";
 133 };
 134
 135 &sata {
 136         status = "okay";
 137         /* SATA phy OOB timing settings */
 138         ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
 139         ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
 140         ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
 141         ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
 142         ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
 143         ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
 144         ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
 145         ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
 146 };
 147
 148 /* eMMC */
 149 &sdhci0 {
 150         status = "okay";
 151         bus-width = <8>;
 152         xlnx,mio_bank = <0>;
 153 };
 154
 155 /* SD1 with level shifter */
 156 &sdhci1 {
 157         status = "okay";
 158         no-1-8-v;       /* for 1.0 silicon */
 159         xlnx,mio_bank = <1>;
 160 };
 161
 162 &uart0 {
 163         status = "okay";
 164 };
 165
 166 /* ULPI SMSC USB3320 */
 167 &usb0 {
 168         status = "okay";
 169 };
 170
 171 &dwc3_0 {
 172         status = "okay";
 173         dr_mode = "host";
 174 };
 175
 176 &xilinx_drm {
 177         status = "okay";
 178 };
 179
 180 &xlnx_dp {
 181         status = "okay";
 182 };
 183
 184 &xlnx_dp_sub {
 185         status = "okay";
 186         xlnx,vid-clk-pl;
 187 };
 188
 189 &xlnx_dp_snd_pcm0 {
 190         status = "okay";
 191 };
 192
 193 &xlnx_dp_snd_pcm1 {
 194         status = "okay";
 195 };
 196
 197 &xlnx_dp_snd_card {
 198         status = "okay";
 199 };
 200
 201 &xlnx_dp_snd_codec0 {
 202         status = "okay";
 203 };
 204
 205 &xlnx_dpdma {
 206         status = "okay";
 207 };