git.sur5r.net Git - u-boot/blob - arch/arm/dts/zynqmp-zcu102-revA.dts

   1 /*
   2  * dts file for Xilinx ZynqMP ZCU102 RevA
   3  *
   4  * (C) Copyright 2015, Xilinx, Inc.
   5  *
   6  * Michal Simek <michal.simek@xilinx.com>
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 /dts-v1/;
  12
  13 #include "zynqmp.dtsi"
  14 #include "zynqmp-clk.dtsi"
  15 #include <dt-bindings/gpio/gpio.h>
  16 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
  17 #include <dt-bindings/phy/phy.h>
  18
  19 / {
  20         model = "ZynqMP ZCU102 RevA";
  21         compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
  22
  23         aliases {
  24                 ethernet0 = &gem3;
  25                 gpio0 = &gpio;
  26                 i2c0 = &i2c0;
  27                 i2c1 = &i2c1;
  28                 mmc0 = &sdhci1;
  29                 rtc0 = &rtc;
  30                 serial0 = &uart0;
  31                 serial1 = &uart1;
  32                 serial2 = &dcc;
  33                 spi0 = &qspi;
  34                 usb0 = &usb0;
  35         };
  36
  37         chosen {
  38                 bootargs = "earlycon";
  39                 stdout-path = "serial0:115200n8";
  40         };
  41
  42         memory@0 {
  43                 device_type = "memory";
  44                 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
  45         };
  46
  47         gpio-keys {
  48                 compatible = "gpio-keys";
  49                 #address-cells = <1>;
  50                 #size-cells = <0>;
  51                 autorepeat;
  52                 sw19 {
  53                         label = "sw19";
  54                         gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
  55                         linux,code = <108>; /* down */
  56                         gpio-key,wakeup;
  57                         autorepeat;
  58                 };
  59         };
  60
  61         leds {
  62                 compatible = "gpio-leds";
  63                 heartbeat_led {
  64                         label = "heartbeat";
  65                         gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
  66                         linux,default-trigger = "heartbeat";
  67                 };
  68         };
  69 };
  70
  71 &can1 {
  72         status = "okay";
  73         pinctrl-names = "default";
  74         pinctrl-0 = <&pinctrl_can1_default>;
  75 };
  76
  77 &dcc {
  78         status = "okay";
  79 };
  80
  81 /* fpd_dma clk 667MHz, lpd_dma 500MHz */
  82 &fpd_dma_chan1 {
  83         status = "okay";
  84 };
  85
  86 &fpd_dma_chan2 {
  87         status = "okay";
  88 };
  89
  90 &fpd_dma_chan3 {
  91         status = "okay";
  92 };
  93
  94 &fpd_dma_chan4 {
  95         status = "okay";
  96 };
  97
  98 &fpd_dma_chan5 {
  99         status = "okay";
 100 };
 101
 102 &fpd_dma_chan6 {
 103         status = "okay";
 104 };
 105
 106 &fpd_dma_chan7 {
 107         status = "okay";
 108 };
 109
 110 &fpd_dma_chan8 {
 111         status = "okay";
 112 };
 113
 114 &gem3 {
 115         status = "okay";
 116         phy-handle = <&phy0>;
 117         phy-mode = "rgmii-id";
 118         pinctrl-names = "default";
 119         pinctrl-0 = <&pinctrl_gem3_default>;
 120         phy0: phy@21 {
 121                 reg = <21>;
 122                 ti,rx-internal-delay = <0x8>;
 123                 ti,tx-internal-delay = <0xa>;
 124                 ti,fifo-depth = <0x1>;
 125         };
 126 };
 127
 128 &gpio {
 129         status = "okay";
 130         pinctrl-names = "default";
 131         pinctrl-0 = <&pinctrl_gpio_default>;
 132 };
 133
 134 &gpu {
 135         status = "okay";
 136 };
 137
 138 &i2c0 {
 139         status = "okay";
 140         clock-frequency = <400000>;
 141         pinctrl-names = "default", "gpio";
 142         pinctrl-0 = <&pinctrl_i2c0_default>;
 143         pinctrl-1 = <&pinctrl_i2c0_gpio>;
 144         scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
 145         sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
 146
 147         tca6416_u97: gpio@20 {
 148                 /*
 149                  * Enable all GTs to out from U-Boot
 150                  * i2c mw 20 6 0  - setup IO to output
 151                  * i2c mw 20 2 ef - setup output values on pins 0-7
 152                  * i2c mw 20 3 ff - setup output values on pins 10-17
 153                  */
 154                 compatible = "ti,tca6416";
 155                 reg = <0x20>;
 156                 gpio-controller;
 157                 #gpio-cells = <2>;
 158                 /*
 159                  * IRQ not connected
 160                  * Lines:
 161                  * 0 - PS_GTR_LAN_SEL0
 162                  * 1 - PS_GTR_LAN_SEL1
 163                  * 2 - PS_GTR_LAN_SEL2
 164                  * 3 - PS_GTR_LAN_SEL3
 165                  * 4 - PCI_CLK_DIR_SEL
 166                  * 5 - IIC_MUX_RESET_B
 167                  * 6 - GEM3_EXP_RESET_B
 168                  * 7, 10 - 17 - not connected
 169                  */
 170
 171                 gtr_sel0 {
 172                         gpio-hog;
 173                         gpios = <0 0>;
 174                         output-low; /* PCIE = 0, DP = 1 */
 175                         line-name = "sel0";
 176                 };
 177                 gtr_sel1 {
 178                         gpio-hog;
 179                         gpios = <1 0>;
 180                         output-high; /* PCIE = 0, DP = 1 */
 181                         line-name = "sel1";
 182                 };
 183                 gtr_sel2 {
 184                         gpio-hog;
 185                         gpios = <2 0>;
 186                         output-high; /* PCIE = 0, USB0 = 1 */
 187                         line-name = "sel2";
 188                 };
 189                 gtr_sel3 {
 190                         gpio-hog;
 191                         gpios = <3 0>;
 192                         output-high; /* PCIE = 0, SATA = 1 */
 193                         line-name = "sel3";
 194                 };
 195         };
 196
 197         tca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */
 198                 compatible = "ti,tca6416";
 199                 reg = <0x21>;
 200                 gpio-controller;
 201                 #gpio-cells = <2>;
 202                 /*
 203                  * IRQ not connected
 204                  * Lines:
 205                  * 0 - VCCPSPLL_EN
 206                  * 1 - MGTRAVCC_EN
 207                  * 2 - MGTRAVTT_EN
 208                  * 3 - VCCPSDDRPLL_EN
 209                  * 4 - MIO26_PMU_INPUT_LS
 210                  * 5 - PL_PMBUS_ALERT
 211                  * 6 - PS_PMBUS_ALERT
 212                  * 7 - MAXIM_PMBUS_ALERT
 213                  * 10 - PL_DDR4_VTERM_EN
 214                  * 11 - PL_DDR4_VPP_2V5_EN
 215                  * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON
 216                  * 13 - PS_DIMM_SUSPEND_EN
 217                  * 14 - PS_DDR4_VTERM_EN
 218                  * 15 - PS_DDR4_VPP_2V5_EN
 219                  * 16 - 17 - not connected
 220                  */
 221         };
 222
 223         i2cswitch@75 { /* u60 */
 224                 compatible = "nxp,pca9544";
 225                 #address-cells = <1>;
 226                 #size-cells = <0>;
 227                 reg = <0x75>;
 228                 i2c@0 { /* i2c mw 75 0 1 */
 229                         #address-cells = <1>;
 230                         #size-cells = <0>;
 231                         reg = <0>;
 232                         /* PS_PMBUS */
 233                         ina226@40 { /* u76 */
 234                                 compatible = "ti,ina226";
 235                                 reg = <0x40>;
 236                                 shunt-resistor = <5000>;
 237                         };
 238                         ina226@41 { /* u77 */
 239                                 compatible = "ti,ina226";
 240                                 reg = <0x41>;
 241                                 shunt-resistor = <5000>;
 242                         };
 243                         ina226@42 { /* u78 */
 244                                 compatible = "ti,ina226";
 245                                 reg = <0x42>;
 246                                 shunt-resistor = <5000>;
 247                         };
 248                         ina226@43 { /* u87 */
 249                                 compatible = "ti,ina226";
 250                                 reg = <0x43>;
 251                                 shunt-resistor = <5000>;
 252                         };
 253                         ina226@44 { /* u85 */
 254                                 compatible = "ti,ina226";
 255                                 reg = <0x44>;
 256                                 shunt-resistor = <5000>;
 257                         };
 258                         ina226@45 { /* u86 */
 259                                 compatible = "ti,ina226";
 260                                 reg = <0x45>;
 261                                 shunt-resistor = <5000>;
 262                         };
 263                         ina226@46 { /* u93 */
 264                                 compatible = "ti,ina226";
 265                                 reg = <0x46>;
 266                                 shunt-resistor = <5000>;
 267                         };
 268                         ina226@47 { /* u88 */
 269                                 compatible = "ti,ina226";
 270                                 reg = <0x47>;
 271                                 shunt-resistor = <5000>;
 272                         };
 273                         ina226@4a { /* u15 */
 274                                 compatible = "ti,ina226";
 275                                 reg = <0x4a>;
 276                                 shunt-resistor = <5000>;
 277                         };
 278                         ina226@4b { /* u92 */
 279                                 compatible = "ti,ina226";
 280                                 reg = <0x4b>;
 281                                 shunt-resistor = <5000>;
 282                         };
 283                 };
 284                 i2c@1 { /* i2c mw 75 0 1 */
 285                         #address-cells = <1>;
 286                         #size-cells = <0>;
 287                         reg = <1>;
 288                         /* PL_PMBUS */
 289                         ina226@40 { /* u79 */
 290                                 compatible = "ti,ina226";
 291                                 reg = <0x40>;
 292                                 shunt-resistor = <2000>;
 293                         };
 294                         ina226@41 { /* u81 */
 295                                 compatible = "ti,ina226";
 296                                 reg = <0x41>;
 297                                 shunt-resistor = <5000>;
 298                         };
 299                         ina226@42 { /* u80 */
 300                                 compatible = "ti,ina226";
 301                                 reg = <0x42>;
 302                                 shunt-resistor = <5000>;
 303                         };
 304                         ina226@43 { /* u84 */
 305                                 compatible = "ti,ina226";
 306                                 reg = <0x43>;
 307                                 shunt-resistor = <5000>;
 308                         };
 309                         ina226@44 { /* u16 */
 310                                 compatible = "ti,ina226";
 311                                 reg = <0x44>;
 312                                 shunt-resistor = <5000>;
 313                         };
 314                         ina226@45 { /* u65 */
 315                                 compatible = "ti,ina226";
 316                                 reg = <0x45>;
 317                                 shunt-resistor = <5000>;
 318                         };
 319                         ina226@46 { /* u74 */
 320                                 compatible = "ti,ina226";
 321                                 reg = <0x46>;
 322                                 shunt-resistor = <5000>;
 323                         };
 324                         ina226@47 { /* u75 */
 325                                 compatible = "ti,ina226";
 326                                 reg = <0x47>;
 327                                 shunt-resistor = <5000>;
 328                         };
 329                 };
 330                 i2c@2 { /* i2c mw 75 0 1 */
 331                         #address-cells = <1>;
 332                         #size-cells = <0>;
 333                         reg = <2>;
 334                         /* MAXIM_PMBUS - 00 */
 335                         max15301@a { /* u46 */
 336                                 compatible = "max15301";
 337                                 reg = <0xa>;
 338                         };
 339                         max15303@b { /* u4 */
 340                                 compatible = "max15303";
 341                                 reg = <0xb>;
 342                         };
 343                         max15303@10 { /* u13 */
 344                                 compatible = "max15303";
 345                                 reg = <0x10>;
 346                         };
 347                         max15301@13 { /* u47 */
 348                                 compatible = "max15301";
 349                                 reg = <0x13>;
 350                         };
 351                         max15303@14 { /* u7 */
 352                                 compatible = "max15303";
 353                                 reg = <0x14>;
 354                         };
 355                         max15303@15 { /* u6 */
 356                                 compatible = "max15303";
 357                                 reg = <0x15>;
 358                         };
 359                         max15303@16 { /* u10 */
 360                                 compatible = "max15303";
 361                                 reg = <0x16>;
 362                         };
 363                         max15303@17 { /* u9 */
 364                                 compatible = "max15303";
 365                                 reg = <0x17>;
 366                         };
 367                         max15301@18 { /* u63 */
 368                                 compatible = "max15301";
 369                                 reg = <0x18>;
 370                         };
 371                         max15303@1a { /* u49 */
 372                                 compatible = "max15303";
 373                                 reg = <0x1a>;
 374                         };
 375                         max15303@1d { /* u18 */
 376                                 compatible = "max15303";
 377                                 reg = <0x1d>;
 378                         };
 379                         max15303@20 { /* u8 */
 380                                 compatible = "max15303";
 381                                 status = "disabled"; /* unreachable */
 382                                 reg = <0x20>;
 383                         };
 384
 385 /*                      drivers/hwmon/pmbus/Kconfig:86:   be called max20751.
 386 drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751)  += max20751.o
 387 */
 388                         max20751@72 { /* u95 FIXME - not detected */
 389                                 compatible = "max20751";
 390                                 reg = <0x72>;
 391                         };
 392                         max20751@73 { /* u96 FIXME - not detected */
 393                                 compatible = "max20751";
 394                                 reg = <0x73>;
 395                         };
 396                 };
 397                 /* Bus 3 is not connected */
 398         };
 399
 400         /* FIXME PMOD - j160 */
 401         /* FIXME MSP430F - u41 - not detected */
 402 };
 403
 404 &i2c1 {
 405         status = "okay";
 406         clock-frequency = <400000>;
 407         pinctrl-names = "default", "gpio";
 408         pinctrl-0 = <&pinctrl_i2c1_default>;
 409         pinctrl-1 = <&pinctrl_i2c1_gpio>;
 410         scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
 411         sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
 412
 413         /* FIXME PL i2c via PCA9306 - u45 */
 414         /* FIXME MSP430 - u41 - not detected */
 415         i2cswitch@74 { /* u34 */
 416                 compatible = "nxp,pca9548";
 417                 #address-cells = <1>;
 418                 #size-cells = <0>;
 419                 reg = <0x74>;
 420                 i2c@0 { /* i2c mw 74 0 1 */
 421                         #address-cells = <1>;
 422                         #size-cells = <0>;
 423                         reg = <0>;
 424                         /*
 425                          * IIC_EEPROM 1kB memory which uses 256B blocks
 426                          * where every block has different address.
 427                          *    0 - 256B address 0x54
 428                          * 256B - 512B address 0x55
 429                          * 512B - 768B address 0x56
 430                          * 768B - 1024B address 0x57
 431                          */
 432                         eeprom: eeprom@54 { /* u23 */
 433                                 compatible = "at,24c08";
 434                                 reg = <0x54>;
 435                         };
 436                 };
 437                 i2c@1 { /* i2c mw 74 0 2 */
 438                         #address-cells = <1>;
 439                         #size-cells = <0>;
 440                         reg = <1>;
 441                         si5341: clock-generator1@36 { /* SI5341 - u69 */
 442                                 compatible = "si5341";
 443                                 reg = <0x36>;
 444                         };
 445
 446                 };
 447                 i2c@2 { /* i2c mw 74 0 4 */
 448                         #address-cells = <1>;
 449                         #size-cells = <0>;
 450                         reg = <2>;
 451                         si570_1: clock-generator2@5d { /* USER SI570 - u42 */
 452                                 #clock-cells = <0>;
 453                                 compatible = "silabs,si570";
 454                                 reg = <0x5d>;
 455                                 temperature-stability = <50>;
 456                                 factory-fout = <300000000>;
 457                                 clock-frequency = <300000000>;
 458                         };
 459                 };
 460                 i2c@3 { /* i2c mw 74 0 8 */
 461                         #address-cells = <1>;
 462                         #size-cells = <0>;
 463                         reg = <3>;
 464                         si570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */
 465                                 #clock-cells = <0>;
 466                                 compatible = "silabs,si570";
 467                                 reg = <0x5d>;
 468                                 temperature-stability = <50>; /* copy from zc702 */
 469                                 factory-fout = <156250000>;
 470                                 clock-frequency = <148500000>;
 471                         };
 472                 };
 473                 i2c@4 { /* i2c mw 74 0 10 */
 474                         #address-cells = <1>;
 475                         #size-cells = <0>;
 476                         reg = <4>;
 477                         si5328: clock-generator4@69 {/* SI5328 - u20 */
 478                                 compatible = "silabs,si5328";
 479                                 reg = <0x69>;
 480                                 /*
 481                                  * Chip has interrupt present connected to PL
 482                                  * interrupt-parent = <&>;
 483                                  * interrupts = <>;
 484                                  */
 485                         };
 486                 };
 487                 /* 5 - 7 unconnected */
 488         };
 489
 490         i2cswitch@75 {
 491                 compatible = "nxp,pca9548"; /* u135 */
 492                 #address-cells = <1>;
 493                 #size-cells = <0>;
 494                 reg = <0x75>;
 495
 496                 i2c@0 {
 497                         #address-cells = <1>;
 498                         #size-cells = <0>;
 499                         reg = <0>;
 500                         /* HPC0_IIC */
 501                 };
 502                 i2c@1 {
 503                         #address-cells = <1>;
 504                         #size-cells = <0>;
 505                         reg = <1>;
 506                         /* HPC1_IIC */
 507                 };
 508                 i2c@2 {
 509                         #address-cells = <1>;
 510                         #size-cells = <0>;
 511                         reg = <2>;
 512                         /* SYSMON */
 513                 };
 514                 i2c@3 { /* i2c mw 75 0 8 */
 515                         #address-cells = <1>;
 516                         #size-cells = <0>;
 517                         reg = <3>;
 518                         /* DDR4 SODIMM */
 519                         dev@19 { /* u-boot detection */
 520                                 compatible = "xxx";
 521                                 reg = <0x19>;
 522                         };
 523                         dev@30 { /* u-boot detection */
 524                                 compatible = "xxx";
 525                                 reg = <0x30>;
 526                         };
 527                         dev@35 { /* u-boot detection */
 528                                 compatible = "xxx";
 529                                 reg = <0x35>;
 530                         };
 531                         dev@36 { /* u-boot detection */
 532                                 compatible = "xxx";
 533                                 reg = <0x36>;
 534                         };
 535                         dev@51 { /* u-boot detection - maybe SPD */
 536                                 compatible = "xxx";
 537                                 reg = <0x51>;
 538                         };
 539                 };
 540                 i2c@4 {
 541                         #address-cells = <1>;
 542                         #size-cells = <0>;
 543                         reg = <4>;
 544                         /* SEP 3 */
 545                 };
 546                 i2c@5 {
 547                         #address-cells = <1>;
 548                         #size-cells = <0>;
 549                         reg = <5>;
 550                         /* SEP 2 */
 551                 };
 552                 i2c@6 {
 553                         #address-cells = <1>;
 554                         #size-cells = <0>;
 555                         reg = <6>;
 556                         /* SEP 1 */
 557                 };
 558                 i2c@7 {
 559                         #address-cells = <1>;
 560                         #size-cells = <0>;
 561                         reg = <7>;
 562                         /* SEP 0 */
 563                 };
 564         };
 565 };
 566
 567 &pinctrl0 {
 568         status = "okay";
 569         pinctrl_i2c0_default: i2c0-default {
 570                 mux {
 571                         groups = "i2c0_3_grp";
 572                         function = "i2c0";
 573                 };
 574
 575                 conf {
 576                         groups = "i2c0_3_grp";
 577                         bias-pull-up;
 578                         slew-rate = <SLEW_RATE_SLOW>;
 579                         io-standard = <IO_STANDARD_LVCMOS18>;
 580                 };
 581         };
 582
 583         pinctrl_i2c0_gpio: i2c0-gpio {
 584                 mux {
 585                         groups = "gpio0_14_grp", "gpio0_15_grp";
 586                         function = "gpio0";
 587                 };
 588
 589                 conf {
 590                         groups = "gpio0_14_grp", "gpio0_15_grp";
 591                         slew-rate = <SLEW_RATE_SLOW>;
 592                         io-standard = <IO_STANDARD_LVCMOS18>;
 593                 };
 594         };
 595
 596         pinctrl_i2c1_default: i2c1-default {
 597                 mux {
 598                         groups = "i2c1_4_grp";
 599                         function = "i2c1";
 600                 };
 601
 602                 conf {
 603                         groups = "i2c1_4_grp";
 604                         bias-pull-up;
 605                         slew-rate = <SLEW_RATE_SLOW>;
 606                         io-standard = <IO_STANDARD_LVCMOS18>;
 607                 };
 608         };
 609
 610         pinctrl_i2c1_gpio: i2c1-gpio {
 611                 mux {
 612                         groups = "gpio0_16_grp", "gpio0_17_grp";
 613                         function = "gpio0";
 614                 };
 615
 616                 conf {
 617                         groups = "gpio0_16_grp", "gpio0_17_grp";
 618                         slew-rate = <SLEW_RATE_SLOW>;
 619                         io-standard = <IO_STANDARD_LVCMOS18>;
 620                 };
 621         };
 622
 623         pinctrl_uart0_default: uart0-default {
 624                 mux {
 625                         groups = "uart0_4_grp";
 626                         function = "uart0";
 627                 };
 628
 629                 conf {
 630                         groups = "uart0_4_grp";
 631                         slew-rate = <SLEW_RATE_SLOW>;
 632                         io-standard = <IO_STANDARD_LVCMOS18>;
 633                 };
 634
 635                 conf-rx {
 636                         pins = "MIO18";
 637                         bias-high-impedance;
 638                 };
 639
 640                 conf-tx {
 641                         pins = "MIO19";
 642                         bias-disable;
 643                 };
 644         };
 645
 646         pinctrl_uart1_default: uart1-default {
 647                 mux {
 648                         groups = "uart1_5_grp";
 649                         function = "uart1";
 650                 };
 651
 652                 conf {
 653                         groups = "uart1_5_grp";
 654                         slew-rate = <SLEW_RATE_SLOW>;
 655                         io-standard = <IO_STANDARD_LVCMOS18>;
 656                 };
 657
 658                 conf-rx {
 659                         pins = "MIO21";
 660                         bias-high-impedance;
 661                 };
 662
 663                 conf-tx {
 664                         pins = "MIO20";
 665                         bias-disable;
 666                 };
 667         };
 668
 669         pinctrl_usb0_default: usb0-default {
 670                 mux {
 671                         groups = "usb0_0_grp";
 672                         function = "usb0";
 673                 };
 674
 675                 conf {
 676                         groups = "usb0_0_grp";
 677                         slew-rate = <SLEW_RATE_SLOW>;
 678                         io-standard = <IO_STANDARD_LVCMOS18>;
 679                 };
 680
 681                 conf-rx {
 682                         pins = "MIO52", "MIO53", "MIO55";
 683                         bias-high-impedance;
 684                 };
 685
 686                 conf-tx {
 687                         pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
 688                                "MIO60", "MIO61", "MIO62", "MIO63";
 689                         bias-disable;
 690                 };
 691         };
 692
 693         pinctrl_gem3_default: gem3-default {
 694                 mux {
 695                         function = "ethernet3";
 696                         groups = "ethernet3_0_grp";
 697                 };
 698
 699                 conf {
 700                         groups = "ethernet3_0_grp";
 701                         slew-rate = <SLEW_RATE_SLOW>;
 702                         io-standard = <IO_STANDARD_LVCMOS18>;
 703                 };
 704
 705                 conf-rx {
 706                         pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
 707                                                                         "MIO75";
 708                         bias-high-impedance;
 709                         low-power-disable;
 710                 };
 711
 712                 conf-tx {
 713                         pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
 714                                                                         "MIO69";
 715                         bias-disable;
 716                         low-power-enable;
 717                 };
 718
 719                 mux-mdio {
 720                         function = "mdio3";
 721                         groups = "mdio3_0_grp";
 722                 };
 723
 724                 conf-mdio {
 725                         groups = "mdio3_0_grp";
 726                         slew-rate = <SLEW_RATE_SLOW>;
 727                         io-standard = <IO_STANDARD_LVCMOS18>;
 728                         bias-disable;
 729                 };
 730         };
 731
 732         pinctrl_can1_default: can1-default {
 733                 mux {
 734                         function = "can1";
 735                         groups = "can1_6_grp";
 736                 };
 737
 738                 conf {
 739                         groups = "can1_6_grp";
 740                         slew-rate = <SLEW_RATE_SLOW>;
 741                         io-standard = <IO_STANDARD_LVCMOS18>;
 742                 };
 743
 744                 conf-rx {
 745                         pins = "MIO25";
 746                         bias-high-impedance;
 747                 };
 748
 749                 conf-tx {
 750                         pins = "MIO24";
 751                         bias-disable;
 752                 };
 753         };
 754
 755         pinctrl_sdhci1_default: sdhci1-default {
 756                 mux {
 757                         groups = "sdio1_0_grp";
 758                         function = "sdio1";
 759                 };
 760
 761                 conf {
 762                         groups = "sdio1_0_grp";
 763                         slew-rate = <SLEW_RATE_SLOW>;
 764                         io-standard = <IO_STANDARD_LVCMOS18>;
 765                         bias-disable;
 766                 };
 767
 768                 mux-cd {
 769                         groups = "sdio1_0_cd_grp";
 770                         function = "sdio1_cd";
 771                 };
 772
 773                 conf-cd {
 774                         groups = "sdio1_0_cd_grp";
 775                         bias-high-impedance;
 776                         bias-pull-up;
 777                         slew-rate = <SLEW_RATE_SLOW>;
 778                         io-standard = <IO_STANDARD_LVCMOS18>;
 779                 };
 780
 781                 mux-wp {
 782                         groups = "sdio1_0_wp_grp";
 783                         function = "sdio1_wp";
 784                 };
 785
 786                 conf-wp {
 787                         groups = "sdio1_0_wp_grp";
 788                         bias-high-impedance;
 789                         bias-pull-up;
 790                         slew-rate = <SLEW_RATE_SLOW>;
 791                         io-standard = <IO_STANDARD_LVCMOS18>;
 792                 };
 793         };
 794
 795         pinctrl_gpio_default: gpio-default {
 796                 mux-sw {
 797                         function = "gpio0";
 798                         groups = "gpio0_22_grp", "gpio0_23_grp";
 799                 };
 800
 801                 conf-sw {
 802                         groups = "gpio0_22_grp", "gpio0_23_grp";
 803                         slew-rate = <SLEW_RATE_SLOW>;
 804                         io-standard = <IO_STANDARD_LVCMOS18>;
 805                 };
 806
 807                 mux-msp {
 808                         function = "gpio0";
 809                         groups = "gpio0_13_grp", "gpio0_38_grp";
 810                 };
 811
 812                 conf-msp {
 813                         groups = "gpio0_13_grp", "gpio0_38_grp";
 814                         slew-rate = <SLEW_RATE_SLOW>;
 815                         io-standard = <IO_STANDARD_LVCMOS18>;
 816                 };
 817
 818                 conf-pull-up {
 819                         pins = "MIO22", "MIO23";
 820                         bias-pull-up;
 821                 };
 822
 823                 conf-pull-none {
 824                         pins = "MIO13", "MIO38";
 825                         bias-disable;
 826                 };
 827         };
 828 };
 829
 830 &pcie {
 831         status = "okay";
 832 };
 833
 834 &qspi {
 835         status = "okay";
 836         is-dual = <1>;
 837         flash@0 {
 838                 compatible = "m25p80"; /* 32MB */
 839                 #address-cells = <1>;
 840                 #size-cells = <1>;
 841                 reg = <0x0>;
 842                 spi-tx-bus-width = <1>;
 843                 spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
 844                 spi-max-frequency = <108000000>; /* Based on DC1 spec */
 845                 partition@qspi-fsbl-uboot { /* for testing purpose */
 846                         label = "qspi-fsbl-uboot";
 847                         reg = <0x0 0x100000>;
 848                 };
 849                 partition@qspi-linux { /* for testing purpose */
 850                         label = "qspi-linux";
 851                         reg = <0x100000 0x500000>;
 852                 };
 853                 partition@qspi-device-tree { /* for testing purpose */
 854                         label = "qspi-device-tree";
 855                         reg = <0x600000 0x20000>;
 856                 };
 857                 partition@qspi-rootfs { /* for testing purpose */
 858                         label = "qspi-rootfs";
 859                         reg = <0x620000 0x5E0000>;
 860                 };
 861         };
 862 };
 863
 864 &rtc {
 865         status = "okay";
 866 };
 867
 868 &sata {
 869         status = "okay";
 870         /* SATA OOB timing settings */
 871         ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
 872         ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
 873         ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
 874         ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
 875         ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
 876         ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
 877         ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
 878         ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
 879         phy-names = "sata-phy";
 880         phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>;
 881 };
 882
 883 /* SD1 with level shifter */
 884 &sdhci1 {
 885         status = "okay";
 886         pinctrl-names = "default";
 887         pinctrl-0 = <&pinctrl_sdhci1_default>;
 888         no-1-8-v;       /* for 1.0 silicon */
 889         xlnx,mio_bank = <1>;
 890 };
 891
 892 &serdes {
 893         status = "okay";
 894 };
 895
 896 &uart0 {
 897         status = "okay";
 898         pinctrl-names = "default";
 899         pinctrl-0 = <&pinctrl_uart0_default>;
 900 };
 901
 902 &uart1 {
 903         status = "okay";
 904         pinctrl-names = "default";
 905         pinctrl-0 = <&pinctrl_uart1_default>;
 906 };
 907
 908 /* ULPI SMSC USB3320 */
 909 &usb0 {
 910         status = "okay";
 911         pinctrl-names = "default";
 912         pinctrl-0 = <&pinctrl_usb0_default>;
 913 };
 914
 915 &dwc3_0 {
 916         status = "okay";
 917         dr_mode = "host";
 918         snps,usb3_lpm_capable;
 919         phy-names = "usb3-phy";
 920         phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;
 921         maximum-speed = "super-speed";
 922 };
 923
 924 &watchdog0 {
 925         status = "okay";
 926 };
 927
 928 &xilinx_ams {
 929         status = "okay";
 930 };
 931
 932 &ams_ps {
 933         status = "okay";
 934 };
 935
 936 &ams_pl {
 937         status = "okay";
 938 };
 939
 940 &xilinx_drm {
 941         status = "okay";
 942         clocks = <&si570_1>;
 943 };
 944
 945 &xlnx_dp {
 946         status = "okay";
 947 };
 948
 949 &xlnx_dp_sub {
 950         status = "okay";
 951         xlnx,vid-clk-pl;
 952 };
 953
 954 &xlnx_dp_snd_pcm0 {
 955         status = "okay";
 956 };
 957
 958 &xlnx_dp_snd_pcm1 {
 959         status = "okay";
 960 };
 961
 962 &xlnx_dp_snd_card {
 963         status = "okay";
 964 };
 965
 966 &xlnx_dp_snd_codec0 {
 967         status = "okay";
 968 };
 969
 970 &xlnx_dpdma {
 971         status = "okay";
 972 };