git.sur5r.net Git - u-boot/blob - arch/arm/dts/zynqmp-zcu102-revA.dts

   1 /*
   2  * dts file for Xilinx ZynqMP ZCU102 RevA
   3  *
   4  * (C) Copyright 2015, Xilinx, Inc.
   5  *
   6  * Michal Simek <michal.simek@xilinx.com>
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 /dts-v1/;
  12
  13 #include "zynqmp.dtsi"
  14 #include "zynqmp-clk.dtsi"
  15 #include <dt-bindings/gpio/gpio.h>
  16 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
  17
  18 / {
  19         model = "ZynqMP ZCU102 RevA";
  20         compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
  21
  22         aliases {
  23                 ethernet0 = &gem3;
  24                 gpio0 = &gpio;
  25                 i2c0 = &i2c0;
  26                 i2c1 = &i2c1;
  27                 mmc0 = &sdhci1;
  28                 rtc0 = &rtc;
  29                 serial0 = &uart0;
  30                 serial1 = &uart1;
  31                 serial2 = &dcc;
  32                 spi0 = &qspi;
  33                 usb0 = &usb0;
  34         };
  35
  36         chosen {
  37                 bootargs = "earlycon";
  38                 stdout-path = "serial0:115200n8";
  39         };
  40
  41         memory@0 {
  42                 device_type = "memory";
  43                 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
  44         };
  45
  46         gpio-keys {
  47                 compatible = "gpio-keys";
  48                 #address-cells = <1>;
  49                 #size-cells = <0>;
  50                 autorepeat;
  51                 sw19 {
  52                         label = "sw19";
  53                         gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
  54                         linux,code = <108>; /* down */
  55                         gpio-key,wakeup;
  56                         autorepeat;
  57                 };
  58         };
  59
  60         leds {
  61                 compatible = "gpio-leds";
  62                 heartbeat_led {
  63                         label = "heartbeat";
  64                         gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
  65                         linux,default-trigger = "heartbeat";
  66                 };
  67         };
  68 };
  69
  70 &can1 {
  71         status = "okay";
  72         pinctrl-names = "default";
  73         pinctrl-0 = <&pinctrl_can1_default>;
  74 };
  75
  76 &dcc {
  77         status = "okay";
  78 };
  79
  80 /* fpd_dma clk 667MHz, lpd_dma 500MHz */
  81 &fpd_dma_chan1 {
  82         status = "okay";
  83         xlnx,include-sg; /* for testing purpose */
  84         xlnx,overfetch; /* for testing purpose */
  85         xlnx,ratectrl = <0>; /* for testing purpose */
  86         xlnx,src-issue = <31>;
  87 };
  88
  89 &fpd_dma_chan2 {
  90         status = "okay";
  91         xlnx,ratectrl = <100>; /* for testing purpose */
  92         xlnx,src-issue = <4>; /* for testing purpose */
  93 };
  94
  95 &fpd_dma_chan3 {
  96         status = "okay";
  97 };
  98
  99 &fpd_dma_chan4 {
 100         status = "okay";
 101         xlnx,include-sg; /* for testing purpose */
 102 };
 103
 104 &fpd_dma_chan5 {
 105         status = "okay";
 106 };
 107
 108 &fpd_dma_chan6 {
 109         status = "okay";
 110         xlnx,include-sg; /* for testing purpose */
 111 };
 112
 113 &fpd_dma_chan7 {
 114         status = "okay";
 115 };
 116
 117 &fpd_dma_chan8 {
 118         status = "okay";
 119         xlnx,include-sg; /* for testing purpose */
 120 };
 121
 122 &gem3 {
 123         status = "okay";
 124         phy-handle = <&phy0>;
 125         phy-mode = "rgmii-id";
 126         pinctrl-names = "default";
 127         pinctrl-0 = <&pinctrl_gem3_default>;
 128         phy0: phy@21 {
 129                 reg = <21>;
 130                 ti,rx-internal-delay = <0x8>;
 131                 ti,tx-internal-delay = <0xa>;
 132                 ti,fifo-depth = <0x1>;
 133         };
 134 };
 135
 136 &gpio {
 137         status = "okay";
 138         pinctrl-names = "default";
 139         pinctrl-0 = <&pinctrl_gpio_default>;
 140 };
 141
 142 &gpu {
 143         status = "okay";
 144 };
 145
 146 &i2c0 {
 147         status = "okay";
 148         clock-frequency = <400000>;
 149         pinctrl-names = "default", "gpio";
 150         pinctrl-0 = <&pinctrl_i2c0_default>;
 151         pinctrl-1 = <&pinctrl_i2c0_gpio>;
 152         scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
 153         sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
 154
 155         tca6416_u97: gpio@20 {
 156                 /*
 157                  * Enable all GTs to out from U-Boot
 158                  * i2c mw 20 6 0  - setup IO to output
 159                  * i2c mw 20 2 ef - setup output values on pins 0-7
 160                  * i2c mw 20 3 ff - setup output values on pins 10-17
 161                  */
 162                 compatible = "ti,tca6416";
 163                 reg = <0x20>;
 164                 gpio-controller;
 165                 #gpio-cells = <2>;
 166                 /*
 167                  * IRQ not connected
 168                  * Lines:
 169                  * 0 - PS_GTR_LAN_SEL0
 170                  * 1 - PS_GTR_LAN_SEL1
 171                  * 2 - PS_GTR_LAN_SEL2
 172                  * 3 - PS_GTR_LAN_SEL3
 173                  * 4 - PCI_CLK_DIR_SEL
 174                  * 5 - IIC_MUX_RESET_B
 175                  * 6 - GEM3_EXP_RESET_B
 176                  * 7, 10 - 17 - not connected
 177                  */
 178
 179                 gtr_sel0 {
 180                         gpio-hog;
 181                         gpios = <0 0>;
 182                         output-low; /* PCIE = 0, DP = 1 */
 183                         line-name = "sel0";
 184                 };
 185                 gtr_sel1 {
 186                         gpio-hog;
 187                         gpios = <1 0>;
 188                         output-high; /* PCIE = 0, DP = 1 */
 189                         line-name = "sel1";
 190                 };
 191                 gtr_sel2 {
 192                         gpio-hog;
 193                         gpios = <2 0>;
 194                         output-high; /* PCIE = 0, USB0 = 1 */
 195                         line-name = "sel2";
 196                 };
 197                 gtr_sel3 {
 198                         gpio-hog;
 199                         gpios = <3 0>;
 200                         output-high; /* PCIE = 0, SATA = 1 */
 201                         line-name = "sel3";
 202                 };
 203         };
 204
 205         tca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */
 206                 compatible = "ti,tca6416";
 207                 reg = <0x21>;
 208                 gpio-controller;
 209                 #gpio-cells = <2>;
 210                 /*
 211                  * IRQ not connected
 212                  * Lines:
 213                  * 0 - VCCPSPLL_EN
 214                  * 1 - MGTRAVCC_EN
 215                  * 2 - MGTRAVTT_EN
 216                  * 3 - VCCPSDDRPLL_EN
 217                  * 4 - MIO26_PMU_INPUT_LS
 218                  * 5 - PL_PMBUS_ALERT
 219                  * 6 - PS_PMBUS_ALERT
 220                  * 7 - MAXIM_PMBUS_ALERT
 221                  * 10 - PL_DDR4_VTERM_EN
 222                  * 11 - PL_DDR4_VPP_2V5_EN
 223                  * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON
 224                  * 13 - PS_DIMM_SUSPEND_EN
 225                  * 14 - PS_DDR4_VTERM_EN
 226                  * 15 - PS_DDR4_VPP_2V5_EN
 227                  * 16 - 17 - not connected
 228                  */
 229         };
 230
 231         i2cswitch@75 { /* u60 */
 232                 compatible = "nxp,pca9544";
 233                 #address-cells = <1>;
 234                 #size-cells = <0>;
 235                 reg = <0x75>;
 236                 i2c@0 { /* i2c mw 75 0 1 */
 237                         #address-cells = <1>;
 238                         #size-cells = <0>;
 239                         reg = <0>;
 240                         /* PS_PMBUS */
 241                         ina226@40 { /* u76 */
 242                                 compatible = "ti,ina226";
 243                                 reg = <0x40>;
 244                                 shunt-resistor = <5000>;
 245                         };
 246                         ina226@41 { /* u77 */
 247                                 compatible = "ti,ina226";
 248                                 reg = <0x41>;
 249                                 shunt-resistor = <5000>;
 250                         };
 251                         ina226@42 { /* u78 */
 252                                 compatible = "ti,ina226";
 253                                 reg = <0x42>;
 254                                 shunt-resistor = <5000>;
 255                         };
 256                         ina226@43 { /* u87 */
 257                                 compatible = "ti,ina226";
 258                                 reg = <0x43>;
 259                                 shunt-resistor = <5000>;
 260                         };
 261                         ina226@44 { /* u85 */
 262                                 compatible = "ti,ina226";
 263                                 reg = <0x44>;
 264                                 shunt-resistor = <5000>;
 265                         };
 266                         ina226@45 { /* u86 */
 267                                 compatible = "ti,ina226";
 268                                 reg = <0x45>;
 269                                 shunt-resistor = <5000>;
 270                         };
 271                         ina226@46 { /* u93 */
 272                                 compatible = "ti,ina226";
 273                                 reg = <0x46>;
 274                                 shunt-resistor = <5000>;
 275                         };
 276                         ina226@47 { /* u88 */
 277                                 compatible = "ti,ina226";
 278                                 reg = <0x47>;
 279                                 shunt-resistor = <5000>;
 280                         };
 281                         ina226@4a { /* u15 */
 282                                 compatible = "ti,ina226";
 283                                 reg = <0x4a>;
 284                                 shunt-resistor = <5000>;
 285                         };
 286                         ina226@4b { /* u92 */
 287                                 compatible = "ti,ina226";
 288                                 reg = <0x4b>;
 289                                 shunt-resistor = <5000>;
 290                         };
 291                 };
 292                 i2c@1 { /* i2c mw 75 0 1 */
 293                         #address-cells = <1>;
 294                         #size-cells = <0>;
 295                         reg = <1>;
 296                         /* PL_PMBUS */
 297                         ina226@40 { /* u79 */
 298                                 compatible = "ti,ina226";
 299                                 reg = <0x40>;
 300                                 shunt-resistor = <2000>;
 301                         };
 302                         ina226@41 { /* u81 */
 303                                 compatible = "ti,ina226";
 304                                 reg = <0x41>;
 305                                 shunt-resistor = <5000>;
 306                         };
 307                         ina226@42 { /* u80 */
 308                                 compatible = "ti,ina226";
 309                                 reg = <0x42>;
 310                                 shunt-resistor = <5000>;
 311                         };
 312                         ina226@43 { /* u84 */
 313                                 compatible = "ti,ina226";
 314                                 reg = <0x43>;
 315                                 shunt-resistor = <5000>;
 316                         };
 317                         ina226@44 { /* u16 */
 318                                 compatible = "ti,ina226";
 319                                 reg = <0x44>;
 320                                 shunt-resistor = <5000>;
 321                         };
 322                         ina226@45 { /* u65 */
 323                                 compatible = "ti,ina226";
 324                                 reg = <0x45>;
 325                                 shunt-resistor = <5000>;
 326                         };
 327                         ina226@46 { /* u74 */
 328                                 compatible = "ti,ina226";
 329                                 reg = <0x46>;
 330                                 shunt-resistor = <5000>;
 331                         };
 332                         ina226@47 { /* u75 */
 333                                 compatible = "ti,ina226";
 334                                 reg = <0x47>;
 335                                 shunt-resistor = <5000>;
 336                         };
 337                 };
 338                 i2c@2 { /* i2c mw 75 0 1 */
 339                         #address-cells = <1>;
 340                         #size-cells = <0>;
 341                         reg = <2>;
 342                         /* MAXIM_PMBUS - 00 */
 343                         max15301@a { /* u46 */
 344                                 compatible = "max15301";
 345                                 reg = <0xa>;
 346                         };
 347                         max15303@b { /* u4 */
 348                                 compatible = "max15303";
 349                                 reg = <0xb>;
 350                         };
 351                         max15303@10 { /* u13 */
 352                                 compatible = "max15303";
 353                                 reg = <0x10>;
 354                         };
 355                         max15301@13 { /* u47 */
 356                                 compatible = "max15301";
 357                                 reg = <0x13>;
 358                         };
 359                         max15303@14 { /* u7 */
 360                                 compatible = "max15303";
 361                                 reg = <0x14>;
 362                         };
 363                         max15303@15 { /* u6 */
 364                                 compatible = "max15303";
 365                                 reg = <0x15>;
 366                         };
 367                         max15303@16 { /* u10 */
 368                                 compatible = "max15303";
 369                                 reg = <0x16>;
 370                         };
 371                         max15303@17 { /* u9 */
 372                                 compatible = "max15303";
 373                                 reg = <0x17>;
 374                         };
 375                         max15301@18 { /* u63 */
 376                                 compatible = "max15301";
 377                                 reg = <0x18>;
 378                         };
 379                         max15303@1a { /* u49 */
 380                                 compatible = "max15303";
 381                                 reg = <0x1a>;
 382                         };
 383                         max15303@1d { /* u18 */
 384                                 compatible = "max15303";
 385                                 reg = <0x1d>;
 386                         };
 387                         max15303@20 { /* u8 */
 388                                 compatible = "max15303";
 389                                 status = "disabled"; /* unreachable */
 390                                 reg = <0x20>;
 391                         };
 392
 393 /*                      drivers/hwmon/pmbus/Kconfig:86:   be called max20751.
 394 drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751)  += max20751.o
 395 */
 396                         max20751@72 { /* u95 FIXME - not detected */
 397                                 compatible = "max20751";
 398                                 reg = <0x72>;
 399                         };
 400                         max20751@73 { /* u96 FIXME - not detected */
 401                                 compatible = "max20751";
 402                                 reg = <0x73>;
 403                         };
 404                 };
 405                 /* Bus 3 is not connected */
 406         };
 407
 408         /* FIXME PMOD - j160 */
 409         /* FIXME MSP430F - u41 - not detected */
 410 };
 411
 412 &i2c1 {
 413         status = "okay";
 414         clock-frequency = <400000>;
 415         pinctrl-names = "default", "gpio";
 416         pinctrl-0 = <&pinctrl_i2c1_default>;
 417         pinctrl-1 = <&pinctrl_i2c1_gpio>;
 418         scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
 419         sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
 420
 421         /* FIXME PL i2c via PCA9306 - u45 */
 422         /* FIXME MSP430 - u41 - not detected */
 423         i2cswitch@74 { /* u34 */
 424                 compatible = "nxp,pca9548";
 425                 #address-cells = <1>;
 426                 #size-cells = <0>;
 427                 reg = <0x74>;
 428                 i2c@0 { /* i2c mw 74 0 1 */
 429                         #address-cells = <1>;
 430                         #size-cells = <0>;
 431                         reg = <0>;
 432                         /*
 433                          * IIC_EEPROM 1kB memory which uses 256B blocks
 434                          * where every block has different address.
 435                          *    0 - 256B address 0x54
 436                          * 256B - 512B address 0x55
 437                          * 512B - 768B address 0x56
 438                          * 768B - 1024B address 0x57
 439                          */
 440                         eeprom: eeprom@54 { /* u23 */
 441                                 compatible = "at,24c08";
 442                                 reg = <0x54>;
 443                         };
 444                 };
 445                 i2c@1 { /* i2c mw 74 0 2 */
 446                         #address-cells = <1>;
 447                         #size-cells = <0>;
 448                         reg = <1>;
 449                         si5341: clock-generator1@36 { /* SI5341 - u69 */
 450                                 compatible = "si5341";
 451                                 reg = <0x36>;
 452                         };
 453
 454                 };
 455                 i2c@2 { /* i2c mw 74 0 4 */
 456                         #address-cells = <1>;
 457                         #size-cells = <0>;
 458                         reg = <2>;
 459                         si570_1: clock-generator2@5d { /* USER SI570 - u42 */
 460                                 #clock-cells = <0>;
 461                                 compatible = "silabs,si570";
 462                                 reg = <0x5d>;
 463                                 temperature-stability = <50>;
 464                                 factory-fout = <300000000>;
 465                                 clock-frequency = <300000000>;
 466                         };
 467                 };
 468                 i2c@3 { /* i2c mw 74 0 8 */
 469                         #address-cells = <1>;
 470                         #size-cells = <0>;
 471                         reg = <3>;
 472                         si570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */
 473                                 #clock-cells = <0>;
 474                                 compatible = "silabs,si570";
 475                                 reg = <0x5d>;
 476                                 temperature-stability = <50>; /* copy from zc702 */
 477                                 factory-fout = <156250000>;
 478                                 clock-frequency = <148500000>;
 479                         };
 480                 };
 481                 i2c@4 { /* i2c mw 74 0 10 */
 482                         #address-cells = <1>;
 483                         #size-cells = <0>;
 484                         reg = <4>;
 485                         si5328: clock-generator4@69 {/* SI5328 - u20 */
 486                                 compatible = "silabs,si5328";
 487                                 reg = <0x69>;
 488                         };
 489                 };
 490                 /* 5 - 7 unconnected */
 491         };
 492
 493         i2cswitch@75 {
 494                 compatible = "nxp,pca9548"; /* u135 */
 495                 #address-cells = <1>;
 496                 #size-cells = <0>;
 497                 reg = <0x75>;
 498
 499                 i2c@0 {
 500                         #address-cells = <1>;
 501                         #size-cells = <0>;
 502                         reg = <0>;
 503                         /* HPC0_IIC */
 504                 };
 505                 i2c@1 {
 506                         #address-cells = <1>;
 507                         #size-cells = <0>;
 508                         reg = <1>;
 509                         /* HPC1_IIC */
 510                 };
 511                 i2c@2 {
 512                         #address-cells = <1>;
 513                         #size-cells = <0>;
 514                         reg = <2>;
 515                         /* SYSMON */
 516                 };
 517                 i2c@3 { /* i2c mw 75 0 8 */
 518                         #address-cells = <1>;
 519                         #size-cells = <0>;
 520                         reg = <3>;
 521                         /* DDR4 SODIMM */
 522                         dev@19 { /* u-boot detection */
 523                                 compatible = "xxx";
 524                                 reg = <0x19>;
 525                         };
 526                         dev@30 { /* u-boot detection */
 527                                 compatible = "xxx";
 528                                 reg = <0x30>;
 529                         };
 530                         dev@35 { /* u-boot detection */
 531                                 compatible = "xxx";
 532                                 reg = <0x35>;
 533                         };
 534                         dev@36 { /* u-boot detection */
 535                                 compatible = "xxx";
 536                                 reg = <0x36>;
 537                         };
 538                         dev@51 { /* u-boot detection - maybe SPD */
 539                                 compatible = "xxx";
 540                                 reg = <0x51>;
 541                         };
 542                 };
 543                 i2c@4 {
 544                         #address-cells = <1>;
 545                         #size-cells = <0>;
 546                         reg = <4>;
 547                         /* SEP 3 */
 548                 };
 549                 i2c@5 {
 550                         #address-cells = <1>;
 551                         #size-cells = <0>;
 552                         reg = <5>;
 553                         /* SEP 2 */
 554                 };
 555                 i2c@6 {
 556                         #address-cells = <1>;
 557                         #size-cells = <0>;
 558                         reg = <6>;
 559                         /* SEP 1 */
 560                 };
 561                 i2c@7 {
 562                         #address-cells = <1>;
 563                         #size-cells = <0>;
 564                         reg = <7>;
 565                         /* SEP 0 */
 566                 };
 567         };
 568 };
 569
 570 &pinctrl0 {
 571         status = "okay";
 572         pinctrl_i2c0_default: i2c0-default {
 573                 mux {
 574                         groups = "i2c0_3_grp";
 575                         function = "i2c0";
 576                 };
 577
 578                 conf {
 579                         groups = "i2c0_3_grp";
 580                         bias-pull-up;
 581                         slew-rate = <SLEW_RATE_SLOW>;
 582                         io-standard = <IO_STANDARD_LVCMOS18>;
 583                 };
 584         };
 585
 586         pinctrl_i2c0_gpio: i2c0-gpio {
 587                 mux {
 588                         groups = "gpio0_14_grp", "gpio0_15_grp";
 589                         function = "gpio0";
 590                 };
 591
 592                 conf {
 593                         groups = "gpio0_14_grp", "gpio0_15_grp";
 594                         slew-rate = <SLEW_RATE_SLOW>;
 595                         io-standard = <IO_STANDARD_LVCMOS18>;
 596                 };
 597         };
 598
 599         pinctrl_i2c1_default: i2c1-default {
 600                 mux {
 601                         groups = "i2c1_4_grp";
 602                         function = "i2c1";
 603                 };
 604
 605                 conf {
 606                         groups = "i2c1_4_grp";
 607                         bias-pull-up;
 608                         slew-rate = <SLEW_RATE_SLOW>;
 609                         io-standard = <IO_STANDARD_LVCMOS18>;
 610                 };
 611         };
 612
 613         pinctrl_i2c1_gpio: i2c1-gpio {
 614                 mux {
 615                         groups = "gpio0_16_grp", "gpio0_17_grp";
 616                         function = "gpio0";
 617                 };
 618
 619                 conf {
 620                         groups = "gpio0_16_grp", "gpio0_17_grp";
 621                         slew-rate = <SLEW_RATE_SLOW>;
 622                         io-standard = <IO_STANDARD_LVCMOS18>;
 623                 };
 624         };
 625
 626         pinctrl_uart0_default: uart0-default {
 627                 mux {
 628                         groups = "uart0_4_grp";
 629                         function = "uart0";
 630                 };
 631
 632                 conf {
 633                         groups = "uart0_4_grp";
 634                         slew-rate = <SLEW_RATE_SLOW>;
 635                         io-standard = <IO_STANDARD_LVCMOS18>;
 636                 };
 637
 638                 conf-rx {
 639                         pins = "MIO18";
 640                         bias-high-impedance;
 641                 };
 642
 643                 conf-tx {
 644                         pins = "MIO19";
 645                         bias-disable;
 646                 };
 647         };
 648
 649         pinctrl_uart1_default: uart1-default {
 650                 mux {
 651                         groups = "uart1_5_grp";
 652                         function = "uart1";
 653                 };
 654
 655                 conf {
 656                         groups = "uart1_5_grp";
 657                         slew-rate = <SLEW_RATE_SLOW>;
 658                         io-standard = <IO_STANDARD_LVCMOS18>;
 659                 };
 660
 661                 conf-rx {
 662                         pins = "MIO21";
 663                         bias-high-impedance;
 664                 };
 665
 666                 conf-tx {
 667                         pins = "MIO20";
 668                         bias-disable;
 669                 };
 670         };
 671
 672         pinctrl_usb0_default: usb0-default {
 673                 mux {
 674                         groups = "usb0_0_grp";
 675                         function = "usb0";
 676                 };
 677
 678                 conf {
 679                         groups = "usb0_0_grp";
 680                         slew-rate = <SLEW_RATE_SLOW>;
 681                         io-standard = <IO_STANDARD_LVCMOS18>;
 682                 };
 683
 684                 conf-rx {
 685                         pins = "MIO52", "MIO53", "MIO55";
 686                         bias-high-impedance;
 687                 };
 688
 689                 conf-tx {
 690                         pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
 691                                "MIO60", "MIO61", "MIO62", "MIO63";
 692                         bias-disable;
 693                 };
 694         };
 695
 696         pinctrl_gem3_default: gem3-default {
 697                 mux {
 698                         function = "ethernet3";
 699                         groups = "ethernet3_0_grp";
 700                 };
 701
 702                 conf {
 703                         groups = "ethernet3_0_grp";
 704                         slew-rate = <SLEW_RATE_SLOW>;
 705                         io-standard = <IO_STANDARD_LVCMOS18>;
 706                 };
 707
 708                 conf-rx {
 709                         pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
 710                                                                         "MIO75";
 711                         bias-high-impedance;
 712                         low-power-disable;
 713                 };
 714
 715                 conf-tx {
 716                         pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
 717                                                                         "MIO69";
 718                         bias-disable;
 719                         low-power-enable;
 720                 };
 721
 722                 mux-mdio {
 723                         function = "mdio3";
 724                         groups = "mdio3_0_grp";
 725                 };
 726
 727                 conf-mdio {
 728                         groups = "mdio3_0_grp";
 729                         slew-rate = <SLEW_RATE_SLOW>;
 730                         io-standard = <IO_STANDARD_LVCMOS18>;
 731                         bias-disable;
 732                 };
 733         };
 734
 735         pinctrl_can1_default: can1-default {
 736                 mux {
 737                         function = "can1";
 738                         groups = "can1_6_grp";
 739                 };
 740
 741                 conf {
 742                         groups = "can1_6_grp";
 743                         slew-rate = <SLEW_RATE_SLOW>;
 744                         io-standard = <IO_STANDARD_LVCMOS18>;
 745                 };
 746
 747                 conf-rx {
 748                         pins = "MIO25";
 749                         bias-high-impedance;
 750                 };
 751
 752                 conf-tx {
 753                         pins = "MIO24";
 754                         bias-disable;
 755                 };
 756         };
 757
 758         pinctrl_sdhci1_default: sdhci1-default {
 759                 mux {
 760                         groups = "sdio1_0_grp";
 761                         function = "sdio1";
 762                 };
 763
 764                 conf {
 765                         groups = "sdio1_0_grp";
 766                         slew-rate = <SLEW_RATE_SLOW>;
 767                         io-standard = <IO_STANDARD_LVCMOS18>;
 768                         bias-disable;
 769                 };
 770
 771                 mux-cd {
 772                         groups = "sdio1_0_cd_grp";
 773                         function = "sdio1_cd";
 774                 };
 775
 776                 conf-cd {
 777                         groups = "sdio1_0_cd_grp";
 778                         bias-high-impedance;
 779                         bias-pull-up;
 780                         slew-rate = <SLEW_RATE_SLOW>;
 781                         io-standard = <IO_STANDARD_LVCMOS18>;
 782                 };
 783
 784                 mux-wp {
 785                         groups = "sdio1_0_wp_grp";
 786                         function = "sdio1_wp";
 787                 };
 788
 789                 conf-wp {
 790                         groups = "sdio1_0_wp_grp";
 791                         bias-high-impedance;
 792                         bias-pull-up;
 793                         slew-rate = <SLEW_RATE_SLOW>;
 794                         io-standard = <IO_STANDARD_LVCMOS18>;
 795                 };
 796         };
 797
 798         pinctrl_gpio_default: gpio-default {
 799                 mux-sw {
 800                         function = "gpio0";
 801                         groups = "gpio0_22_grp", "gpio0_23_grp";
 802                 };
 803
 804                 conf-sw {
 805                         groups = "gpio0_22_grp", "gpio0_23_grp";
 806                         slew-rate = <SLEW_RATE_SLOW>;
 807                         io-standard = <IO_STANDARD_LVCMOS18>;
 808                 };
 809
 810                 mux-msp {
 811                         function = "gpio0";
 812                         groups = "gpio0_13_grp", "gpio0_38_grp";
 813                 };
 814
 815                 conf-msp {
 816                         groups = "gpio0_13_grp", "gpio0_38_grp";
 817                         slew-rate = <SLEW_RATE_SLOW>;
 818                         io-standard = <IO_STANDARD_LVCMOS18>;
 819                 };
 820
 821                 conf-pull-up {
 822                         pins = "MIO22", "MIO23";
 823                         bias-pull-up;
 824                 };
 825
 826                 conf-pull-none {
 827                         pins = "MIO13", "MIO38";
 828                         bias-disable;
 829                 };
 830         };
 831 };
 832
 833 &pcie {
 834         status = "okay";
 835 };
 836
 837 &qspi {
 838         status = "okay";
 839         is-dual = <1>;
 840         flash@0 {
 841                 compatible = "m25p80"; /* 32MB */
 842                 #address-cells = <1>;
 843                 #size-cells = <1>;
 844                 reg = <0x0>;
 845                 spi-tx-bus-width = <1>;
 846                 spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
 847                 spi-max-frequency = <108000000>; /* Based on DC1 spec */
 848                 partition@qspi-fsbl-uboot { /* for testing purpose */
 849                         label = "qspi-fsbl-uboot";
 850                         reg = <0x0 0x100000>;
 851                 };
 852                 partition@qspi-linux { /* for testing purpose */
 853                         label = "qspi-linux";
 854                         reg = <0x100000 0x500000>;
 855                 };
 856                 partition@qspi-device-tree { /* for testing purpose */
 857                         label = "qspi-device-tree";
 858                         reg = <0x600000 0x20000>;
 859                 };
 860                 partition@qspi-rootfs { /* for testing purpose */
 861                         label = "qspi-rootfs";
 862                         reg = <0x620000 0x5E0000>;
 863                 };
 864         };
 865 };
 866
 867 &rtc {
 868         status = "okay";
 869 };
 870
 871 &sata {
 872         status = "okay";
 873         /* SATA OOB timing settings */
 874         ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
 875         ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
 876         ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
 877         ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
 878         ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
 879         ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
 880         ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
 881         ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
 882 };
 883
 884 /* SD1 with level shifter */
 885 &sdhci1 {
 886         status = "okay";
 887         pinctrl-names = "default";
 888         pinctrl-0 = <&pinctrl_sdhci1_default>;
 889         no-1-8-v;       /* for 1.0 silicon */
 890         xlnx,mio_bank = <1>;
 891 };
 892
 893 &uart0 {
 894         status = "okay";
 895         pinctrl-names = "default";
 896         pinctrl-0 = <&pinctrl_uart0_default>;
 897 };
 898
 899 &uart1 {
 900         status = "okay";
 901         pinctrl-names = "default";
 902         pinctrl-0 = <&pinctrl_uart1_default>;
 903 };
 904
 905 /* ULPI SMSC USB3320 */
 906 &usb0 {
 907         status = "okay";
 908         pinctrl-names = "default";
 909         pinctrl-0 = <&pinctrl_usb0_default>;
 910 };
 911
 912 &dwc3_0 {
 913         status = "okay";
 914         dr_mode = "host";
 915 };
 916
 917 &xilinx_ams {
 918         status = "okay";
 919 };
 920
 921 &ams_ps {
 922         status = "okay";
 923 };
 924
 925 &ams_pl {
 926         status = "okay";
 927 };
 928
 929 &xilinx_drm {
 930         status = "okay";
 931         clocks = <&si570_1>;
 932 };
 933
 934 &xlnx_dp {
 935         status = "okay";
 936 };
 937
 938 &xlnx_dp_sub {
 939         status = "okay";
 940         xlnx,vid-clk-pl;
 941 };
 942
 943 &xlnx_dp_snd_pcm0 {
 944         status = "okay";
 945 };
 946
 947 &xlnx_dp_snd_pcm1 {
 948         status = "okay";
 949 };
 950
 951 &xlnx_dp_snd_card {
 952         status = "okay";
 953 };
 954
 955 &xlnx_dp_snd_codec0 {
 956         status = "okay";
 957 };
 958
 959 &xlnx_dpdma {
 960         status = "okay";
 961 };