git.sur5r.net Git - u-boot/blob - arch/arm/dts/zynqmp-zcu102-revA.dts

   1 /*
   2  * dts file for Xilinx ZynqMP ZCU102 RevA
   3  *
   4  * (C) Copyright 2015, Xilinx, Inc.
   5  *
   6  * Michal Simek <michal.simek@xilinx.com>
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 /dts-v1/;
  12
  13 #include "zynqmp.dtsi"
  14 #include "zynqmp-clk.dtsi"
  15 #include <dt-bindings/gpio/gpio.h>
  16 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
  17 #include <dt-bindings/phy/phy.h>
  18
  19 / {
  20         model = "ZynqMP ZCU102 RevA";
  21         compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
  22
  23         aliases {
  24                 ethernet0 = &gem3;
  25                 gpio0 = &gpio;
  26                 i2c0 = &i2c0;
  27                 i2c1 = &i2c1;
  28                 mmc0 = &sdhci1;
  29                 rtc0 = &rtc;
  30                 serial0 = &uart0;
  31                 serial1 = &uart1;
  32                 serial2 = &dcc;
  33                 spi0 = &qspi;
  34                 usb0 = &usb0;
  35         };
  36
  37         chosen {
  38                 bootargs = "earlycon";
  39                 stdout-path = "serial0:115200n8";
  40         };
  41
  42         memory@0 {
  43                 device_type = "memory";
  44                 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
  45         };
  46
  47         gpio-keys {
  48                 compatible = "gpio-keys";
  49                 #address-cells = <1>;
  50                 #size-cells = <0>;
  51                 autorepeat;
  52                 sw19 {
  53                         label = "sw19";
  54                         gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
  55                         linux,code = <108>; /* down */
  56                         gpio-key,wakeup;
  57                         autorepeat;
  58                 };
  59         };
  60
  61         leds {
  62                 compatible = "gpio-leds";
  63                 heartbeat_led {
  64                         label = "heartbeat";
  65                         gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
  66                         linux,default-trigger = "heartbeat";
  67                 };
  68         };
  69 };
  70
  71 &can1 {
  72         status = "okay";
  73         pinctrl-names = "default";
  74         pinctrl-0 = <&pinctrl_can1_default>;
  75 };
  76
  77 &dcc {
  78         status = "okay";
  79 };
  80
  81 /* fpd_dma clk 667MHz, lpd_dma 500MHz */
  82 &fpd_dma_chan1 {
  83         status = "okay";
  84         xlnx,include-sg; /* for testing purpose */
  85         xlnx,overfetch; /* for testing purpose */
  86         xlnx,ratectrl = <0>; /* for testing purpose */
  87         xlnx,src-issue = <31>;
  88 };
  89
  90 &fpd_dma_chan2 {
  91         status = "okay";
  92         xlnx,ratectrl = <100>; /* for testing purpose */
  93         xlnx,src-issue = <4>; /* for testing purpose */
  94 };
  95
  96 &fpd_dma_chan3 {
  97         status = "okay";
  98 };
  99
 100 &fpd_dma_chan4 {
 101         status = "okay";
 102         xlnx,include-sg; /* for testing purpose */
 103 };
 104
 105 &fpd_dma_chan5 {
 106         status = "okay";
 107 };
 108
 109 &fpd_dma_chan6 {
 110         status = "okay";
 111         xlnx,include-sg; /* for testing purpose */
 112 };
 113
 114 &fpd_dma_chan7 {
 115         status = "okay";
 116 };
 117
 118 &fpd_dma_chan8 {
 119         status = "okay";
 120         xlnx,include-sg; /* for testing purpose */
 121 };
 122
 123 &gem3 {
 124         status = "okay";
 125         phy-handle = <&phy0>;
 126         phy-mode = "rgmii-id";
 127         pinctrl-names = "default";
 128         pinctrl-0 = <&pinctrl_gem3_default>;
 129         phy0: phy@21 {
 130                 reg = <21>;
 131                 ti,rx-internal-delay = <0x8>;
 132                 ti,tx-internal-delay = <0xa>;
 133                 ti,fifo-depth = <0x1>;
 134         };
 135 };
 136
 137 &gpio {
 138         status = "okay";
 139         pinctrl-names = "default";
 140         pinctrl-0 = <&pinctrl_gpio_default>;
 141 };
 142
 143 &gpu {
 144         status = "okay";
 145 };
 146
 147 &i2c0 {
 148         status = "okay";
 149         clock-frequency = <400000>;
 150         pinctrl-names = "default", "gpio";
 151         pinctrl-0 = <&pinctrl_i2c0_default>;
 152         pinctrl-1 = <&pinctrl_i2c0_gpio>;
 153         scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
 154         sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
 155
 156         tca6416_u97: gpio@20 {
 157                 /*
 158                  * Enable all GTs to out from U-Boot
 159                  * i2c mw 20 6 0  - setup IO to output
 160                  * i2c mw 20 2 ef - setup output values on pins 0-7
 161                  * i2c mw 20 3 ff - setup output values on pins 10-17
 162                  */
 163                 compatible = "ti,tca6416";
 164                 reg = <0x20>;
 165                 gpio-controller;
 166                 #gpio-cells = <2>;
 167                 /*
 168                  * IRQ not connected
 169                  * Lines:
 170                  * 0 - PS_GTR_LAN_SEL0
 171                  * 1 - PS_GTR_LAN_SEL1
 172                  * 2 - PS_GTR_LAN_SEL2
 173                  * 3 - PS_GTR_LAN_SEL3
 174                  * 4 - PCI_CLK_DIR_SEL
 175                  * 5 - IIC_MUX_RESET_B
 176                  * 6 - GEM3_EXP_RESET_B
 177                  * 7, 10 - 17 - not connected
 178                  */
 179
 180                 gtr_sel0 {
 181                         gpio-hog;
 182                         gpios = <0 0>;
 183                         output-low; /* PCIE = 0, DP = 1 */
 184                         line-name = "sel0";
 185                 };
 186                 gtr_sel1 {
 187                         gpio-hog;
 188                         gpios = <1 0>;
 189                         output-high; /* PCIE = 0, DP = 1 */
 190                         line-name = "sel1";
 191                 };
 192                 gtr_sel2 {
 193                         gpio-hog;
 194                         gpios = <2 0>;
 195                         output-high; /* PCIE = 0, USB0 = 1 */
 196                         line-name = "sel2";
 197                 };
 198                 gtr_sel3 {
 199                         gpio-hog;
 200                         gpios = <3 0>;
 201                         output-high; /* PCIE = 0, SATA = 1 */
 202                         line-name = "sel3";
 203                 };
 204         };
 205
 206         tca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */
 207                 compatible = "ti,tca6416";
 208                 reg = <0x21>;
 209                 gpio-controller;
 210                 #gpio-cells = <2>;
 211                 /*
 212                  * IRQ not connected
 213                  * Lines:
 214                  * 0 - VCCPSPLL_EN
 215                  * 1 - MGTRAVCC_EN
 216                  * 2 - MGTRAVTT_EN
 217                  * 3 - VCCPSDDRPLL_EN
 218                  * 4 - MIO26_PMU_INPUT_LS
 219                  * 5 - PL_PMBUS_ALERT
 220                  * 6 - PS_PMBUS_ALERT
 221                  * 7 - MAXIM_PMBUS_ALERT
 222                  * 10 - PL_DDR4_VTERM_EN
 223                  * 11 - PL_DDR4_VPP_2V5_EN
 224                  * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON
 225                  * 13 - PS_DIMM_SUSPEND_EN
 226                  * 14 - PS_DDR4_VTERM_EN
 227                  * 15 - PS_DDR4_VPP_2V5_EN
 228                  * 16 - 17 - not connected
 229                  */
 230         };
 231
 232         i2cswitch@75 { /* u60 */
 233                 compatible = "nxp,pca9544";
 234                 #address-cells = <1>;
 235                 #size-cells = <0>;
 236                 reg = <0x75>;
 237                 i2c@0 { /* i2c mw 75 0 1 */
 238                         #address-cells = <1>;
 239                         #size-cells = <0>;
 240                         reg = <0>;
 241                         /* PS_PMBUS */
 242                         ina226@40 { /* u76 */
 243                                 compatible = "ti,ina226";
 244                                 reg = <0x40>;
 245                                 shunt-resistor = <5000>;
 246                         };
 247                         ina226@41 { /* u77 */
 248                                 compatible = "ti,ina226";
 249                                 reg = <0x41>;
 250                                 shunt-resistor = <5000>;
 251                         };
 252                         ina226@42 { /* u78 */
 253                                 compatible = "ti,ina226";
 254                                 reg = <0x42>;
 255                                 shunt-resistor = <5000>;
 256                         };
 257                         ina226@43 { /* u87 */
 258                                 compatible = "ti,ina226";
 259                                 reg = <0x43>;
 260                                 shunt-resistor = <5000>;
 261                         };
 262                         ina226@44 { /* u85 */
 263                                 compatible = "ti,ina226";
 264                                 reg = <0x44>;
 265                                 shunt-resistor = <5000>;
 266                         };
 267                         ina226@45 { /* u86 */
 268                                 compatible = "ti,ina226";
 269                                 reg = <0x45>;
 270                                 shunt-resistor = <5000>;
 271                         };
 272                         ina226@46 { /* u93 */
 273                                 compatible = "ti,ina226";
 274                                 reg = <0x46>;
 275                                 shunt-resistor = <5000>;
 276                         };
 277                         ina226@47 { /* u88 */
 278                                 compatible = "ti,ina226";
 279                                 reg = <0x47>;
 280                                 shunt-resistor = <5000>;
 281                         };
 282                         ina226@4a { /* u15 */
 283                                 compatible = "ti,ina226";
 284                                 reg = <0x4a>;
 285                                 shunt-resistor = <5000>;
 286                         };
 287                         ina226@4b { /* u92 */
 288                                 compatible = "ti,ina226";
 289                                 reg = <0x4b>;
 290                                 shunt-resistor = <5000>;
 291                         };
 292                 };
 293                 i2c@1 { /* i2c mw 75 0 1 */
 294                         #address-cells = <1>;
 295                         #size-cells = <0>;
 296                         reg = <1>;
 297                         /* PL_PMBUS */
 298                         ina226@40 { /* u79 */
 299                                 compatible = "ti,ina226";
 300                                 reg = <0x40>;
 301                                 shunt-resistor = <2000>;
 302                         };
 303                         ina226@41 { /* u81 */
 304                                 compatible = "ti,ina226";
 305                                 reg = <0x41>;
 306                                 shunt-resistor = <5000>;
 307                         };
 308                         ina226@42 { /* u80 */
 309                                 compatible = "ti,ina226";
 310                                 reg = <0x42>;
 311                                 shunt-resistor = <5000>;
 312                         };
 313                         ina226@43 { /* u84 */
 314                                 compatible = "ti,ina226";
 315                                 reg = <0x43>;
 316                                 shunt-resistor = <5000>;
 317                         };
 318                         ina226@44 { /* u16 */
 319                                 compatible = "ti,ina226";
 320                                 reg = <0x44>;
 321                                 shunt-resistor = <5000>;
 322                         };
 323                         ina226@45 { /* u65 */
 324                                 compatible = "ti,ina226";
 325                                 reg = <0x45>;
 326                                 shunt-resistor = <5000>;
 327                         };
 328                         ina226@46 { /* u74 */
 329                                 compatible = "ti,ina226";
 330                                 reg = <0x46>;
 331                                 shunt-resistor = <5000>;
 332                         };
 333                         ina226@47 { /* u75 */
 334                                 compatible = "ti,ina226";
 335                                 reg = <0x47>;
 336                                 shunt-resistor = <5000>;
 337                         };
 338                 };
 339                 i2c@2 { /* i2c mw 75 0 1 */
 340                         #address-cells = <1>;
 341                         #size-cells = <0>;
 342                         reg = <2>;
 343                         /* MAXIM_PMBUS - 00 */
 344                         max15301@a { /* u46 */
 345                                 compatible = "max15301";
 346                                 reg = <0xa>;
 347                         };
 348                         max15303@b { /* u4 */
 349                                 compatible = "max15303";
 350                                 reg = <0xb>;
 351                         };
 352                         max15303@10 { /* u13 */
 353                                 compatible = "max15303";
 354                                 reg = <0x10>;
 355                         };
 356                         max15301@13 { /* u47 */
 357                                 compatible = "max15301";
 358                                 reg = <0x13>;
 359                         };
 360                         max15303@14 { /* u7 */
 361                                 compatible = "max15303";
 362                                 reg = <0x14>;
 363                         };
 364                         max15303@15 { /* u6 */
 365                                 compatible = "max15303";
 366                                 reg = <0x15>;
 367                         };
 368                         max15303@16 { /* u10 */
 369                                 compatible = "max15303";
 370                                 reg = <0x16>;
 371                         };
 372                         max15303@17 { /* u9 */
 373                                 compatible = "max15303";
 374                                 reg = <0x17>;
 375                         };
 376                         max15301@18 { /* u63 */
 377                                 compatible = "max15301";
 378                                 reg = <0x18>;
 379                         };
 380                         max15303@1a { /* u49 */
 381                                 compatible = "max15303";
 382                                 reg = <0x1a>;
 383                         };
 384                         max15303@1d { /* u18 */
 385                                 compatible = "max15303";
 386                                 reg = <0x1d>;
 387                         };
 388                         max15303@20 { /* u8 */
 389                                 compatible = "max15303";
 390                                 status = "disabled"; /* unreachable */
 391                                 reg = <0x20>;
 392                         };
 393
 394 /*                      drivers/hwmon/pmbus/Kconfig:86:   be called max20751.
 395 drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751)  += max20751.o
 396 */
 397                         max20751@72 { /* u95 FIXME - not detected */
 398                                 compatible = "max20751";
 399                                 reg = <0x72>;
 400                         };
 401                         max20751@73 { /* u96 FIXME - not detected */
 402                                 compatible = "max20751";
 403                                 reg = <0x73>;
 404                         };
 405                 };
 406                 /* Bus 3 is not connected */
 407         };
 408
 409         /* FIXME PMOD - j160 */
 410         /* FIXME MSP430F - u41 - not detected */
 411 };
 412
 413 &i2c1 {
 414         status = "okay";
 415         clock-frequency = <400000>;
 416         pinctrl-names = "default", "gpio";
 417         pinctrl-0 = <&pinctrl_i2c1_default>;
 418         pinctrl-1 = <&pinctrl_i2c1_gpio>;
 419         scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
 420         sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
 421
 422         /* FIXME PL i2c via PCA9306 - u45 */
 423         /* FIXME MSP430 - u41 - not detected */
 424         i2cswitch@74 { /* u34 */
 425                 compatible = "nxp,pca9548";
 426                 #address-cells = <1>;
 427                 #size-cells = <0>;
 428                 reg = <0x74>;
 429                 i2c@0 { /* i2c mw 74 0 1 */
 430                         #address-cells = <1>;
 431                         #size-cells = <0>;
 432                         reg = <0>;
 433                         /*
 434                          * IIC_EEPROM 1kB memory which uses 256B blocks
 435                          * where every block has different address.
 436                          *    0 - 256B address 0x54
 437                          * 256B - 512B address 0x55
 438                          * 512B - 768B address 0x56
 439                          * 768B - 1024B address 0x57
 440                          */
 441                         eeprom: eeprom@54 { /* u23 */
 442                                 compatible = "at,24c08";
 443                                 reg = <0x54>;
 444                         };
 445                 };
 446                 i2c@1 { /* i2c mw 74 0 2 */
 447                         #address-cells = <1>;
 448                         #size-cells = <0>;
 449                         reg = <1>;
 450                         si5341: clock-generator1@36 { /* SI5341 - u69 */
 451                                 compatible = "si5341";
 452                                 reg = <0x36>;
 453                         };
 454
 455                 };
 456                 i2c@2 { /* i2c mw 74 0 4 */
 457                         #address-cells = <1>;
 458                         #size-cells = <0>;
 459                         reg = <2>;
 460                         si570_1: clock-generator2@5d { /* USER SI570 - u42 */
 461                                 #clock-cells = <0>;
 462                                 compatible = "silabs,si570";
 463                                 reg = <0x5d>;
 464                                 temperature-stability = <50>;
 465                                 factory-fout = <300000000>;
 466                                 clock-frequency = <300000000>;
 467                         };
 468                 };
 469                 i2c@3 { /* i2c mw 74 0 8 */
 470                         #address-cells = <1>;
 471                         #size-cells = <0>;
 472                         reg = <3>;
 473                         si570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */
 474                                 #clock-cells = <0>;
 475                                 compatible = "silabs,si570";
 476                                 reg = <0x5d>;
 477                                 temperature-stability = <50>; /* copy from zc702 */
 478                                 factory-fout = <156250000>;
 479                                 clock-frequency = <148500000>;
 480                         };
 481                 };
 482                 i2c@4 { /* i2c mw 74 0 10 */
 483                         #address-cells = <1>;
 484                         #size-cells = <0>;
 485                         reg = <4>;
 486                         si5328: clock-generator4@69 {/* SI5328 - u20 */
 487                                 compatible = "silabs,si5328";
 488                                 reg = <0x69>;
 489                                 /*
 490                                  * Chip has interrupt present connected to PL
 491                                  * interrupt-parent = <&>;
 492                                  * interrupts = <>;
 493                                  */
 494                         };
 495                 };
 496                 /* 5 - 7 unconnected */
 497         };
 498
 499         i2cswitch@75 {
 500                 compatible = "nxp,pca9548"; /* u135 */
 501                 #address-cells = <1>;
 502                 #size-cells = <0>;
 503                 reg = <0x75>;
 504
 505                 i2c@0 {
 506                         #address-cells = <1>;
 507                         #size-cells = <0>;
 508                         reg = <0>;
 509                         /* HPC0_IIC */
 510                 };
 511                 i2c@1 {
 512                         #address-cells = <1>;
 513                         #size-cells = <0>;
 514                         reg = <1>;
 515                         /* HPC1_IIC */
 516                 };
 517                 i2c@2 {
 518                         #address-cells = <1>;
 519                         #size-cells = <0>;
 520                         reg = <2>;
 521                         /* SYSMON */
 522                 };
 523                 i2c@3 { /* i2c mw 75 0 8 */
 524                         #address-cells = <1>;
 525                         #size-cells = <0>;
 526                         reg = <3>;
 527                         /* DDR4 SODIMM */
 528                         dev@19 { /* u-boot detection */
 529                                 compatible = "xxx";
 530                                 reg = <0x19>;
 531                         };
 532                         dev@30 { /* u-boot detection */
 533                                 compatible = "xxx";
 534                                 reg = <0x30>;
 535                         };
 536                         dev@35 { /* u-boot detection */
 537                                 compatible = "xxx";
 538                                 reg = <0x35>;
 539                         };
 540                         dev@36 { /* u-boot detection */
 541                                 compatible = "xxx";
 542                                 reg = <0x36>;
 543                         };
 544                         dev@51 { /* u-boot detection - maybe SPD */
 545                                 compatible = "xxx";
 546                                 reg = <0x51>;
 547                         };
 548                 };
 549                 i2c@4 {
 550                         #address-cells = <1>;
 551                         #size-cells = <0>;
 552                         reg = <4>;
 553                         /* SEP 3 */
 554                 };
 555                 i2c@5 {
 556                         #address-cells = <1>;
 557                         #size-cells = <0>;
 558                         reg = <5>;
 559                         /* SEP 2 */
 560                 };
 561                 i2c@6 {
 562                         #address-cells = <1>;
 563                         #size-cells = <0>;
 564                         reg = <6>;
 565                         /* SEP 1 */
 566                 };
 567                 i2c@7 {
 568                         #address-cells = <1>;
 569                         #size-cells = <0>;
 570                         reg = <7>;
 571                         /* SEP 0 */
 572                 };
 573         };
 574 };
 575
 576 &pinctrl0 {
 577         status = "okay";
 578         pinctrl_i2c0_default: i2c0-default {
 579                 mux {
 580                         groups = "i2c0_3_grp";
 581                         function = "i2c0";
 582                 };
 583
 584                 conf {
 585                         groups = "i2c0_3_grp";
 586                         bias-pull-up;
 587                         slew-rate = <SLEW_RATE_SLOW>;
 588                         io-standard = <IO_STANDARD_LVCMOS18>;
 589                 };
 590         };
 591
 592         pinctrl_i2c0_gpio: i2c0-gpio {
 593                 mux {
 594                         groups = "gpio0_14_grp", "gpio0_15_grp";
 595                         function = "gpio0";
 596                 };
 597
 598                 conf {
 599                         groups = "gpio0_14_grp", "gpio0_15_grp";
 600                         slew-rate = <SLEW_RATE_SLOW>;
 601                         io-standard = <IO_STANDARD_LVCMOS18>;
 602                 };
 603         };
 604
 605         pinctrl_i2c1_default: i2c1-default {
 606                 mux {
 607                         groups = "i2c1_4_grp";
 608                         function = "i2c1";
 609                 };
 610
 611                 conf {
 612                         groups = "i2c1_4_grp";
 613                         bias-pull-up;
 614                         slew-rate = <SLEW_RATE_SLOW>;
 615                         io-standard = <IO_STANDARD_LVCMOS18>;
 616                 };
 617         };
 618
 619         pinctrl_i2c1_gpio: i2c1-gpio {
 620                 mux {
 621                         groups = "gpio0_16_grp", "gpio0_17_grp";
 622                         function = "gpio0";
 623                 };
 624
 625                 conf {
 626                         groups = "gpio0_16_grp", "gpio0_17_grp";
 627                         slew-rate = <SLEW_RATE_SLOW>;
 628                         io-standard = <IO_STANDARD_LVCMOS18>;
 629                 };
 630         };
 631
 632         pinctrl_uart0_default: uart0-default {
 633                 mux {
 634                         groups = "uart0_4_grp";
 635                         function = "uart0";
 636                 };
 637
 638                 conf {
 639                         groups = "uart0_4_grp";
 640                         slew-rate = <SLEW_RATE_SLOW>;
 641                         io-standard = <IO_STANDARD_LVCMOS18>;
 642                 };
 643
 644                 conf-rx {
 645                         pins = "MIO18";
 646                         bias-high-impedance;
 647                 };
 648
 649                 conf-tx {
 650                         pins = "MIO19";
 651                         bias-disable;
 652                 };
 653         };
 654
 655         pinctrl_uart1_default: uart1-default {
 656                 mux {
 657                         groups = "uart1_5_grp";
 658                         function = "uart1";
 659                 };
 660
 661                 conf {
 662                         groups = "uart1_5_grp";
 663                         slew-rate = <SLEW_RATE_SLOW>;
 664                         io-standard = <IO_STANDARD_LVCMOS18>;
 665                 };
 666
 667                 conf-rx {
 668                         pins = "MIO21";
 669                         bias-high-impedance;
 670                 };
 671
 672                 conf-tx {
 673                         pins = "MIO20";
 674                         bias-disable;
 675                 };
 676         };
 677
 678         pinctrl_usb0_default: usb0-default {
 679                 mux {
 680                         groups = "usb0_0_grp";
 681                         function = "usb0";
 682                 };
 683
 684                 conf {
 685                         groups = "usb0_0_grp";
 686                         slew-rate = <SLEW_RATE_SLOW>;
 687                         io-standard = <IO_STANDARD_LVCMOS18>;
 688                 };
 689
 690                 conf-rx {
 691                         pins = "MIO52", "MIO53", "MIO55";
 692                         bias-high-impedance;
 693                 };
 694
 695                 conf-tx {
 696                         pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
 697                                "MIO60", "MIO61", "MIO62", "MIO63";
 698                         bias-disable;
 699                 };
 700         };
 701
 702         pinctrl_gem3_default: gem3-default {
 703                 mux {
 704                         function = "ethernet3";
 705                         groups = "ethernet3_0_grp";
 706                 };
 707
 708                 conf {
 709                         groups = "ethernet3_0_grp";
 710                         slew-rate = <SLEW_RATE_SLOW>;
 711                         io-standard = <IO_STANDARD_LVCMOS18>;
 712                 };
 713
 714                 conf-rx {
 715                         pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
 716                                                                         "MIO75";
 717                         bias-high-impedance;
 718                         low-power-disable;
 719                 };
 720
 721                 conf-tx {
 722                         pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
 723                                                                         "MIO69";
 724                         bias-disable;
 725                         low-power-enable;
 726                 };
 727
 728                 mux-mdio {
 729                         function = "mdio3";
 730                         groups = "mdio3_0_grp";
 731                 };
 732
 733                 conf-mdio {
 734                         groups = "mdio3_0_grp";
 735                         slew-rate = <SLEW_RATE_SLOW>;
 736                         io-standard = <IO_STANDARD_LVCMOS18>;
 737                         bias-disable;
 738                 };
 739         };
 740
 741         pinctrl_can1_default: can1-default {
 742                 mux {
 743                         function = "can1";
 744                         groups = "can1_6_grp";
 745                 };
 746
 747                 conf {
 748                         groups = "can1_6_grp";
 749                         slew-rate = <SLEW_RATE_SLOW>;
 750                         io-standard = <IO_STANDARD_LVCMOS18>;
 751                 };
 752
 753                 conf-rx {
 754                         pins = "MIO25";
 755                         bias-high-impedance;
 756                 };
 757
 758                 conf-tx {
 759                         pins = "MIO24";
 760                         bias-disable;
 761                 };
 762         };
 763
 764         pinctrl_sdhci1_default: sdhci1-default {
 765                 mux {
 766                         groups = "sdio1_0_grp";
 767                         function = "sdio1";
 768                 };
 769
 770                 conf {
 771                         groups = "sdio1_0_grp";
 772                         slew-rate = <SLEW_RATE_SLOW>;
 773                         io-standard = <IO_STANDARD_LVCMOS18>;
 774                         bias-disable;
 775                 };
 776
 777                 mux-cd {
 778                         groups = "sdio1_0_cd_grp";
 779                         function = "sdio1_cd";
 780                 };
 781
 782                 conf-cd {
 783                         groups = "sdio1_0_cd_grp";
 784                         bias-high-impedance;
 785                         bias-pull-up;
 786                         slew-rate = <SLEW_RATE_SLOW>;
 787                         io-standard = <IO_STANDARD_LVCMOS18>;
 788                 };
 789
 790                 mux-wp {
 791                         groups = "sdio1_0_wp_grp";
 792                         function = "sdio1_wp";
 793                 };
 794
 795                 conf-wp {
 796                         groups = "sdio1_0_wp_grp";
 797                         bias-high-impedance;
 798                         bias-pull-up;
 799                         slew-rate = <SLEW_RATE_SLOW>;
 800                         io-standard = <IO_STANDARD_LVCMOS18>;
 801                 };
 802         };
 803
 804         pinctrl_gpio_default: gpio-default {
 805                 mux-sw {
 806                         function = "gpio0";
 807                         groups = "gpio0_22_grp", "gpio0_23_grp";
 808                 };
 809
 810                 conf-sw {
 811                         groups = "gpio0_22_grp", "gpio0_23_grp";
 812                         slew-rate = <SLEW_RATE_SLOW>;
 813                         io-standard = <IO_STANDARD_LVCMOS18>;
 814                 };
 815
 816                 mux-msp {
 817                         function = "gpio0";
 818                         groups = "gpio0_13_grp", "gpio0_38_grp";
 819                 };
 820
 821                 conf-msp {
 822                         groups = "gpio0_13_grp", "gpio0_38_grp";
 823                         slew-rate = <SLEW_RATE_SLOW>;
 824                         io-standard = <IO_STANDARD_LVCMOS18>;
 825                 };
 826
 827                 conf-pull-up {
 828                         pins = "MIO22", "MIO23";
 829                         bias-pull-up;
 830                 };
 831
 832                 conf-pull-none {
 833                         pins = "MIO13", "MIO38";
 834                         bias-disable;
 835                 };
 836         };
 837 };
 838
 839 &pcie {
 840         status = "okay";
 841 };
 842
 843 &qspi {
 844         status = "okay";
 845         is-dual = <1>;
 846         flash@0 {
 847                 compatible = "m25p80"; /* 32MB */
 848                 #address-cells = <1>;
 849                 #size-cells = <1>;
 850                 reg = <0x0>;
 851                 spi-tx-bus-width = <1>;
 852                 spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
 853                 spi-max-frequency = <108000000>; /* Based on DC1 spec */
 854                 partition@qspi-fsbl-uboot { /* for testing purpose */
 855                         label = "qspi-fsbl-uboot";
 856                         reg = <0x0 0x100000>;
 857                 };
 858                 partition@qspi-linux { /* for testing purpose */
 859                         label = "qspi-linux";
 860                         reg = <0x100000 0x500000>;
 861                 };
 862                 partition@qspi-device-tree { /* for testing purpose */
 863                         label = "qspi-device-tree";
 864                         reg = <0x600000 0x20000>;
 865                 };
 866                 partition@qspi-rootfs { /* for testing purpose */
 867                         label = "qspi-rootfs";
 868                         reg = <0x620000 0x5E0000>;
 869                 };
 870         };
 871 };
 872
 873 &rtc {
 874         status = "okay";
 875 };
 876
 877 &sata {
 878         status = "okay";
 879         /* SATA OOB timing settings */
 880         ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
 881         ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
 882         ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
 883         ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
 884         ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
 885         ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
 886         ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
 887         ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
 888         phy-names = "sata-phy";
 889         phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>;
 890 };
 891
 892 /* SD1 with level shifter */
 893 &sdhci1 {
 894         status = "okay";
 895         pinctrl-names = "default";
 896         pinctrl-0 = <&pinctrl_sdhci1_default>;
 897         no-1-8-v;       /* for 1.0 silicon */
 898         xlnx,mio_bank = <1>;
 899 };
 900
 901 &serdes {
 902         status = "okay";
 903 };
 904
 905 &uart0 {
 906         status = "okay";
 907         pinctrl-names = "default";
 908         pinctrl-0 = <&pinctrl_uart0_default>;
 909 };
 910
 911 &uart1 {
 912         status = "okay";
 913         pinctrl-names = "default";
 914         pinctrl-0 = <&pinctrl_uart1_default>;
 915 };
 916
 917 /* ULPI SMSC USB3320 */
 918 &usb0 {
 919         status = "okay";
 920         pinctrl-names = "default";
 921         pinctrl-0 = <&pinctrl_usb0_default>;
 922 };
 923
 924 &dwc3_0 {
 925         status = "okay";
 926         dr_mode = "host";
 927         snps,usb3_lpm_capable;
 928         phy-names = "usb3-phy";
 929         phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;
 930         maximum-speed = "super-speed";
 931 };
 932
 933 &watchdog0 {
 934         status = "okay";
 935 };
 936
 937 &xilinx_ams {
 938         status = "okay";
 939 };
 940
 941 &ams_ps {
 942         status = "okay";
 943 };
 944
 945 &ams_pl {
 946         status = "okay";
 947 };
 948
 949 &xilinx_drm {
 950         status = "okay";
 951         clocks = <&si570_1>;
 952 };
 953
 954 &xlnx_dp {
 955         status = "okay";
 956 };
 957
 958 &xlnx_dp_sub {
 959         status = "okay";
 960         xlnx,vid-clk-pl;
 961 };
 962
 963 &xlnx_dp_snd_pcm0 {
 964         status = "okay";
 965 };
 966
 967 &xlnx_dp_snd_pcm1 {
 968         status = "okay";
 969 };
 970
 971 &xlnx_dp_snd_card {
 972         status = "okay";
 973 };
 974
 975 &xlnx_dp_snd_codec0 {
 976         status = "okay";
 977 };
 978
 979 &xlnx_dpdma {
 980         status = "okay";
 981 };