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arm: socfpga: Fix typos in DT files (environmnet -> environment)
[u-boot] / arch / arm / dts / zynqmp-zcu102.dts
1 /*
2  * dts file for Xilinx ZynqMP ZCU102
3  *
4  * (C) Copyright 2015, Xilinx, Inc.
5  *
6  * Michal Simek <michal.simek@xilinx.com>
7  *
8  * SPDX-License-Identifier:     GPL-2.0+
9  */
10
11 /dts-v1/;
12
13 #include "zynqmp.dtsi"
14 #include "zynqmp-clk.dtsi"
15
16 / {
17         model = "ZynqMP ZCU102 RevA";
18         compatible = "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
19
20         aliases {
21                 ethernet0 = &gem3;
22                 gpio0 = &gpio;
23                 i2c0 = &i2c0;
24                 i2c1 = &i2c1;
25                 mmc0 = &sdhci1;
26                 rtc0 = &rtc;
27                 serial0 = &uart0;
28                 serial1 = &uart1;
29                 spi0 = &qspi;
30                 usb0 = &usb0;
31         };
32
33         chosen {
34                 bootargs = "earlycon";
35                 stdout-path = "serial0:115200n8";
36         };
37
38         memory {
39                 device_type = "memory";
40                 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
41         };
42 };
43
44 &can1 {
45         status = "okay";
46 };
47
48 /* fpd_dma clk 667MHz, lpd_dma 500MHz */
49 &fpd_dma_chan1 {
50         status = "okay";
51         xlnx,include-sg; /* for testing purpose */
52         xlnx,overfetch; /* for testing purpose */
53         xlnx,ratectrl = <0>; /* for testing purpose */
54         xlnx,src-issue = <31>;
55 };
56
57 &fpd_dma_chan2 {
58         status = "okay";
59         xlnx,ratectrl = <100>; /* for testing purpose */
60         xlnx,src-issue = <4>; /* for testing purpose */
61 };
62
63 &fpd_dma_chan3 {
64         status = "okay";
65 };
66
67 &fpd_dma_chan4 {
68         status = "okay";
69         xlnx,include-sg; /* for testing purpose */
70 };
71
72 &fpd_dma_chan5 {
73         status = "okay";
74 };
75
76 &fpd_dma_chan6 {
77         status = "okay";
78         xlnx,include-sg; /* for testing purpose */
79 };
80
81 &fpd_dma_chan7 {
82         status = "okay";
83 };
84
85 &fpd_dma_chan8 {
86         status = "okay";
87         xlnx,include-sg; /* for testing purpose */
88 };
89
90 &gem3 {
91         status = "okay";
92         local-mac-address = [00 0a 35 00 02 90];
93         phy-handle = <&phy0>;
94         phy-mode = "rgmii-id";
95         phy0: phy@21 {
96                 reg = <21>;
97                 ti,rx-internal-delay = <0x8>;
98                 ti,tx-internal-delay = <0xa>;
99                 ti,fifo-depth = <0x1>;
100         };
101 };
102
103 &gpio {
104         status = "okay";
105 };
106
107 &gpu {
108         status = "okay";
109 };
110
111 &i2c0 {
112         status = "okay";
113         clock-frequency = <400000>;
114
115         tca6416_u97: gpio@20 {
116                 /*
117                  * Enable all GTs to out from U-Boot
118                  * i2c mw 20 6 0  - setup IO to output
119                  * i2c mw 20 2 ef - setup output values on pins 0-7
120                  * i2c mw 20 3 ff - setup output values on pins 10-17
121                  */
122                 compatible = "ti,tca6416";
123                 reg = <0x20>;
124                 gpio-controller;
125                 #gpio-cells = <2>;
126                 /*
127                  * IRQ not connected
128                  * Lines:
129                  * 0 - PS_GTR_LAN_SEL0
130                  * 1 - PS_GTR_LAN_SEL1
131                  * 2 - PS_GTR_LAN_SEL2
132                  * 3 - PS_GTR_LAN_SEL3
133                  * 4 - PCI_CLK_DIR_SEL
134                  * 5 - IIC_MUX_RESET_B
135                  * 6 - GEM3_EXP_RESET_B
136                  * 7, 10 - 17 - not connected
137                  */
138
139                 gtr_sel0 {
140                         gpio-hog;
141                         gpios = <0 0>;
142                         output-high; /* PCIE = 0, DP = 1 */
143                         line-name = "sel0";
144                 };
145                 gtr_sel1 {
146                         gpio-hog;
147                         gpios = <1 0>;
148                         output-high; /* PCIE = 0, DP = 1 */
149                         line-name = "sel1";
150                 };
151                 gtr_sel2 {
152                         gpio-hog;
153                         gpios = <2 0>;
154                         output-high; /* PCIE = 0, USB0 = 1 */
155                         line-name = "sel2";
156                 };
157                 gtr_sel3 {
158                         gpio-hog;
159                         gpios = <3 0>;
160                         output-high; /* PCIE = 0, SATA = 1 */
161                         line-name = "sel3";
162                 };
163         };
164
165         tca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */
166                 compatible = "ti,tca6416";
167                 reg = <0x21>;
168                 gpio-controller;
169                 #gpio-cells = <2>;
170                 /*
171                  * IRQ not connected
172                  * Lines:
173                  * 0 - VCCPSPLL_EN
174                  * 1 - MGTRAVCC_EN
175                  * 2 - MGTRAVTT_EN
176                  * 3 - VCCPSDDRPLL_EN
177                  * 4 - MIO26_PMU_INPUT_LS
178                  * 5 - PL_PMBUS_ALERT
179                  * 6 - PS_PMBUS_ALERT
180                  * 7 - MAXIM_PMBUS_ALERT
181                  * 10 - PL_DDR4_VTERM_EN
182                  * 11 - PL_DDR4_VPP_2V5_EN
183                  * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON
184                  * 13 - PS_DIMM_SUSPEND_EN
185                  * 14 - PS_DDR4_VTERM_EN
186                  * 15 - PS_DDR4_VPP_2V5_EN
187                  * 16 - 17 - not connected
188                  */
189         };
190
191         i2cswitch@75 { /* u60 */
192                 compatible = "nxp,pca9544";
193                 #address-cells = <1>;
194                 #size-cells = <0>;
195                 reg = <0x75>;
196                 i2c@0 { /* i2c mw 75 0 1 */
197                         #address-cells = <1>;
198                         #size-cells = <0>;
199                         reg = <0>;
200                         /* PS_PMBUS */
201                         ina226@40 { /* u76 */
202                                 compatible = "ti,ina226";
203                                 reg = <0x40>;
204                                 shunt-resistor = <5000>;
205                         };
206                         ina226@41 { /* u77 */
207                                 compatible = "ti,ina226";
208                                 reg = <0x41>;
209                                 shunt-resistor = <5000>;
210                         };
211                         ina226@42 { /* u78 */
212                                 compatible = "ti,ina226";
213                                 reg = <0x42>;
214                                 shunt-resistor = <5000>;
215                         };
216                         ina226@43 { /* u87 */
217                                 compatible = "ti,ina226";
218                                 reg = <0x43>;
219                                 shunt-resistor = <5000>;
220                         };
221                         ina226@44 { /* u85 */
222                                 compatible = "ti,ina226";
223                                 reg = <0x44>;
224                                 shunt-resistor = <5000>;
225                         };
226                         ina226@45 { /* u86 */
227                                 compatible = "ti,ina226";
228                                 reg = <0x45>;
229                                 shunt-resistor = <5000>;
230                         };
231                         ina226@46 { /* u93 */
232                                 compatible = "ti,ina226";
233                                 reg = <0x46>;
234                                 shunt-resistor = <5000>;
235                         };
236                         ina226@47 { /* u88 */
237                                 compatible = "ti,ina226";
238                                 reg = <0x47>;
239                                 shunt-resistor = <5000>;
240                         };
241                         ina226@4a { /* u15 */
242                                 compatible = "ti,ina226";
243                                 reg = <0x4a>;
244                                 shunt-resistor = <5000>;
245                         };
246                         ina226@4b { /* u92 */
247                                 compatible = "ti,ina226";
248                                 reg = <0x4b>;
249                                 shunt-resistor = <5000>;
250                         };
251                 };
252                 i2c@1 { /* i2c mw 75 0 1 */
253                         #address-cells = <1>;
254                         #size-cells = <0>;
255                         reg = <1>;
256                         /* PL_PMBUS */
257                         ina226@40 { /* u79 */
258                                 compatible = "ti,ina226";
259                                 reg = <0x40>;
260                                 shunt-resistor = <2000>;
261                         };
262                         ina226@41 { /* u81 */
263                                 compatible = "ti,ina226";
264                                 reg = <0x41>;
265                                 shunt-resistor = <5000>;
266                         };
267                         ina226@42 { /* u80 */
268                                 compatible = "ti,ina226";
269                                 reg = <0x42>;
270                                 shunt-resistor = <5000>;
271                         };
272                         ina226@43 { /* u84 */
273                                 compatible = "ti,ina226";
274                                 reg = <0x43>;
275                                 shunt-resistor = <5000>;
276                         };
277                         ina226@44 { /* u16 */
278                                 compatible = "ti,ina226";
279                                 reg = <0x44>;
280                                 shunt-resistor = <5000>;
281                         };
282                         ina226@45 { /* u65 */
283                                 compatible = "ti,ina226";
284                                 reg = <0x45>;
285                                 shunt-resistor = <5000>;
286                         };
287                         ina226@46 { /* u74 */
288                                 compatible = "ti,ina226";
289                                 reg = <0x46>;
290                                 shunt-resistor = <5000>;
291                         };
292                         ina226@47 { /* u75 */
293                                 compatible = "ti,ina226";
294                                 reg = <0x47>;
295                                 shunt-resistor = <5000>;
296                         };
297                 };
298                 i2c@2 { /* i2c mw 75 0 1 */
299                         #address-cells = <1>;
300                         #size-cells = <0>;
301                         reg = <2>;
302                         /* MAXIM_PMBUS - 00 */
303                         max15301@a { /* u46 */
304                                 compatible = "max15301";
305                                 reg = <0xa>;
306                         };
307                         max15303@b { /* u4 */
308                                 compatible = "max15303";
309                                 reg = <0xb>;
310                         };
311                         max15303@10 { /* u13 */
312                                 compatible = "max15303";
313                                 reg = <0x10>;
314                         };
315                         max15301@13 { /* u47 */
316                                 compatible = "max15301";
317                                 reg = <0x13>;
318                         };
319                         max15303@14 { /* u7 */
320                                 compatible = "max15303";
321                                 reg = <0x14>;
322                         };
323                         max15303@15 { /* u6 */
324                                 compatible = "max15303";
325                                 reg = <0x15>;
326                         };
327                         max15303@16 { /* u10 */
328                                 compatible = "max15303";
329                                 reg = <0x16>;
330                         };
331                         max15303@17 { /* u9 */
332                                 compatible = "max15303";
333                                 reg = <0x17>;
334                         };
335                         max15301@18 { /* u63 */
336                                 compatible = "max15301";
337                                 reg = <0x18>;
338                         };
339                         max15303@1a { /* u49 */
340                                 compatible = "max15303";
341                                 reg = <0x1a>;
342                         };
343                         max15303@1d { /* u18 */
344                                 compatible = "max15303";
345                                 reg = <0x1d>;
346                         };
347                         max15303@20 { /* u8 */
348                                 compatible = "max15303";
349                                 status = "disabled"; /* unreachable */
350                                 reg = <0x20>;
351                         };
352
353 /*                      drivers/hwmon/pmbus/Kconfig:86:   be called max20751.
354 drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751)  += max20751.o
355 */
356                         max20751@72 { /* u95 FIXME - not detected */
357                                 compatible = "max20751";
358                                 reg = <0x72>;
359                         };
360                         max20751@73 { /* u96 FIXME - not detected */
361                                 compatible = "max20751";
362                                 reg = <0x73>;
363                         };
364                 };
365                 /* Bus 3 is not connected */
366         };
367
368         /* FIXME PL connection - u55 , PMOD - j160 */
369         /* FIXME MSP430F - u41 - not detected */
370 };
371
372 &i2c1 {
373         status = "okay";
374         clock-frequency = <400000>;
375         /* FIXME PL i2c via PCA9306 - u45 */
376         /* FIXME MSP430 - u41 - not detected */
377         i2cswitch@74 { /* u34 */
378                 compatible = "nxp,pca9548";
379                 #address-cells = <1>;
380                 #size-cells = <0>;
381                 reg = <0x74>;
382                 i2c@0 { /* i2c mw 74 0 1 */
383                         #address-cells = <1>;
384                         #size-cells = <0>;
385                         reg = <0>;
386                         /*
387                          * IIC_EEPROM 1kB memory which uses 256B blocks
388                          * where every block has different address.
389                          *    0 - 256B address 0x54
390                          * 256B - 512B address 0x55
391                          * 512B - 768B address 0x56
392                          * 768B - 1024B address 0x57
393                          */
394                         eeprom@54 { /* u23 */
395                                 compatible = "at,24c08";
396                                 reg = <0x54>;
397                         };
398                 };
399                 i2c@1 { /* i2c mw 74 0 2 */
400                         #address-cells = <1>;
401                         #size-cells = <0>;
402                         reg = <1>;
403                         si5341: clock-generator1@36 { /* SI5341 - u69 */
404                                 compatible = "si5341";
405                                 reg = <0x36>;
406                         };
407
408                 };
409                 i2c@2 { /* i2c mw 74 0 4 */
410                         #address-cells = <1>;
411                         #size-cells = <0>;
412                         reg = <2>;
413                         si570_1: clock-generator2@5d { /* USER SI570 - u42 */
414                                 #clock-cells = <0>;
415                                 compatible = "silabs,si570";
416                                 reg = <0x5d>;
417                                 temperature-stability = <50>;
418                                 factory-fout = <300000000>;
419                                 clock-frequency = <300000000>;
420                         };
421                 };
422                 i2c@3 { /* i2c mw 74 0 8 */
423                         #address-cells = <1>;
424                         #size-cells = <0>;
425                         reg = <3>;
426                         si570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */
427                                 #clock-cells = <0>;
428                                 compatible = "silabs,si570";
429                                 reg = <0x5d>;
430                                 temperature-stability = <50>; /* copy from zc702 */
431                                 factory-fout = <156250000>;
432                                 clock-frequency = <148500000>;
433                         };
434                 };
435                 i2c@4 { /* i2c mw 74 0 10 */
436                         #address-cells = <1>;
437                         #size-cells = <0>;
438                         reg = <4>;
439                         si5328: clock-generator4@69 {/* SI5328 - u20 */
440                                 compatible = "silabs,si5328";
441                                 reg = <0x69>;
442                         };
443                 };
444                 /* 5 - 7 unconnected */
445         };
446
447         i2cswitch@75 {
448                 compatible = "nxp,pca9548"; /* u135 */
449                 #address-cells = <1>;
450                 #size-cells = <0>;
451                 reg = <0x75>;
452
453                 i2c@0 {
454                         #address-cells = <1>;
455                         #size-cells = <0>;
456                         reg = <0>;
457                         /* HPC0_IIC */
458                 };
459                 i2c@1 {
460                         #address-cells = <1>;
461                         #size-cells = <0>;
462                         reg = <1>;
463                         /* HPC1_IIC */
464                 };
465                 i2c@2 {
466                         #address-cells = <1>;
467                         #size-cells = <0>;
468                         reg = <2>;
469                         /* SYSMON */
470                 };
471                 i2c@3 { /* i2c mw 75 0 8 */
472                         #address-cells = <1>;
473                         #size-cells = <0>;
474                         reg = <3>;
475                         /* DDR4 SODIMM */
476                         dev@19 { /* u-boot detection */
477                                 compatible = "xxx";
478                                 reg = <0x19>;
479                         };
480                         dev@30 { /* u-boot detection */
481                                 compatible = "xxx";
482                                 reg = <0x30>;
483                         };
484                         dev@35 { /* u-boot detection */
485                                 compatible = "xxx";
486                                 reg = <0x35>;
487                         };
488                         dev@36 { /* u-boot detection */
489                                 compatible = "xxx";
490                                 reg = <0x36>;
491                         };
492                         dev@51 { /* u-boot detection - maybe SPD */
493                                 compatible = "xxx";
494                                 reg = <0x51>;
495                         };
496                 };
497                 i2c@4 {
498                         #address-cells = <1>;
499                         #size-cells = <0>;
500                         reg = <4>;
501                         /* SEP 3 */
502                 };
503                 i2c@5 {
504                         #address-cells = <1>;
505                         #size-cells = <0>;
506                         reg = <5>;
507                         /* SEP 2 */
508                 };
509                 i2c@6 {
510                         #address-cells = <1>;
511                         #size-cells = <0>;
512                         reg = <6>;
513                         /* SEP 1 */
514                 };
515                 i2c@7 {
516                         #address-cells = <1>;
517                         #size-cells = <0>;
518                         reg = <7>;
519                         /* SEP 0 */
520                 };
521         };
522 };
523
524 &pcie {
525 /*      status = "okay"; */
526 };
527
528 &qspi {
529         status = "okay";
530         is-dual = <1>;
531         flash@0 {
532                 compatible = "m25p80"; /* 32MB */
533                 #address-cells = <1>;
534                 #size-cells = <1>;
535                 reg = <0x0>;
536                 spi-tx-bus-width = <1>;
537                 spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
538                 spi-max-frequency = <108000000>; /* Based on DC1 spec */
539                 partition@qspi-fsbl-uboot { /* for testing purpose */
540                         label = "qspi-fsbl-uboot";
541                         reg = <0x0 0x100000>;
542                 };
543                 partition@qspi-linux { /* for testing purpose */
544                         label = "qspi-linux";
545                         reg = <0x100000 0x500000>;
546                 };
547                 partition@qspi-device-tree { /* for testing purpose */
548                         label = "qspi-device-tree";
549                         reg = <0x600000 0x20000>;
550                 };
551                 partition@qspi-rootfs { /* for testing purpose */
552                         label = "qspi-rootfs";
553                         reg = <0x620000 0x5E0000>;
554                 };
555         };
556 };
557
558 &rtc {
559         status = "okay";
560 };
561
562 &sata {
563         status = "okay";
564         /* SATA OOB timing settings */
565         ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
566         ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
567         ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
568         ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
569         ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
570         ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
571         ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
572         ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
573 };
574
575 /* SD1 with level shifter */
576 &sdhci1 {
577         status = "okay";
578         no-1-8-v;       /* for 1.0 silicon */
579 };
580
581 &uart0 {
582         status = "okay";
583 };
584
585 &uart1 {
586         status = "okay";
587 };
588
589 /* ULPI SMSC USB3320 */
590 &usb0 {
591         status = "okay";
592 };
593
594 &dwc3_0 {
595         status = "okay";
596         dr_mode = "host";
597 };
598
599 &xilinx_drm {
600         status = "okay";
601         clocks = <&si570_1>;
602 };
603
604 &xlnx_dp {
605         status = "okay";
606 };
607
608 &xlnx_dp_sub {
609         status = "okay";
610         xlnx,vid-clk-pl;
611 };
612
613 &xlnx_dp_snd_pcm0 {
614         status = "okay";
615 };
616
617 &xlnx_dp_snd_pcm1 {
618         status = "okay";
619 };
620
621 &xlnx_dp_snd_card {
622         status = "okay";
623 };
624
625 &xlnx_dp_snd_codec0 {
626         status = "okay";
627 };
628
629 &xlnx_dpdma {
630         status = "okay";
631 };