git.sur5r.net Git - u-boot/blob - arch/arm/dts/zynqmp-zcu102.dts

   1 /*
   2  * dts file for Xilinx ZynqMP ZCU102
   3  *
   4  * (C) Copyright 2015, Xilinx, Inc.
   5  *
   6  * Michal Simek <michal.simek@xilinx.com>
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 /dts-v1/;
  12
  13 #include "zynqmp.dtsi"
  14 #include "zynqmp-clk.dtsi"
  15 #include <dt-bindings/gpio/gpio.h>
  16
  17 / {
  18         model = "ZynqMP ZCU102 RevA";
  19         compatible = "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
  20
  21         aliases {
  22                 ethernet0 = &gem3;
  23                 gpio0 = &gpio;
  24                 i2c0 = &i2c0;
  25                 i2c1 = &i2c1;
  26                 mmc0 = &sdhci1;
  27                 rtc0 = &rtc;
  28                 serial0 = &uart0;
  29                 serial1 = &uart1;
  30                 spi0 = &qspi;
  31                 usb0 = &usb0;
  32         };
  33
  34         chosen {
  35                 bootargs = "earlycon";
  36                 stdout-path = "serial0:115200n8";
  37         };
  38
  39         memory@0 {
  40                 device_type = "memory";
  41                 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
  42         };
  43
  44         gpio-keys {
  45                 compatible = "gpio-keys";
  46                 #address-cells = <1>;
  47                 #size-cells = <0>;
  48                 autorepeat;
  49                 sw19 {
  50                         label = "sw19";
  51                         gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
  52                         linux,code = <108>; /* down */
  53                         gpio-key,wakeup;
  54                         autorepeat;
  55                 };
  56         };
  57
  58         leds {
  59                 compatible = "gpio-leds";
  60                 heartbeat_led {
  61                         label = "heartbeat";
  62                         gpios = <&gpio 23 0>;
  63                         linux,default-trigger = "heartbeat";
  64                 };
  65         };
  66 };
  67
  68 &can1 {
  69         status = "okay";
  70 };
  71
  72 /* fpd_dma clk 667MHz, lpd_dma 500MHz */
  73 &fpd_dma_chan1 {
  74         status = "okay";
  75         xlnx,include-sg; /* for testing purpose */
  76         xlnx,overfetch; /* for testing purpose */
  77         xlnx,ratectrl = <0>; /* for testing purpose */
  78         xlnx,src-issue = <31>;
  79 };
  80
  81 &fpd_dma_chan2 {
  82         status = "okay";
  83         xlnx,ratectrl = <100>; /* for testing purpose */
  84         xlnx,src-issue = <4>; /* for testing purpose */
  85 };
  86
  87 &fpd_dma_chan3 {
  88         status = "okay";
  89 };
  90
  91 &fpd_dma_chan4 {
  92         status = "okay";
  93         xlnx,include-sg; /* for testing purpose */
  94 };
  95
  96 &fpd_dma_chan5 {
  97         status = "okay";
  98 };
  99
 100 &fpd_dma_chan6 {
 101         status = "okay";
 102         xlnx,include-sg; /* for testing purpose */
 103 };
 104
 105 &fpd_dma_chan7 {
 106         status = "okay";
 107 };
 108
 109 &fpd_dma_chan8 {
 110         status = "okay";
 111         xlnx,include-sg; /* for testing purpose */
 112 };
 113
 114 &gem3 {
 115         status = "okay";
 116         local-mac-address = [00 0a 35 00 02 90];
 117         phy-handle = <&phy0>;
 118         phy-mode = "rgmii-id";
 119         phy0: phy@21 {
 120                 reg = <21>;
 121                 ti,rx-internal-delay = <0x8>;
 122                 ti,tx-internal-delay = <0xa>;
 123                 ti,fifo-depth = <0x1>;
 124         };
 125 };
 126
 127 &gpio {
 128         status = "okay";
 129 };
 130
 131 &gpu {
 132         status = "okay";
 133 };
 134
 135 &i2c0 {
 136         status = "okay";
 137         clock-frequency = <400000>;
 138
 139         tca6416_u97: gpio@20 {
 140                 /*
 141                  * Enable all GTs to out from U-Boot
 142                  * i2c mw 20 6 0  - setup IO to output
 143                  * i2c mw 20 2 ef - setup output values on pins 0-7
 144                  * i2c mw 20 3 ff - setup output values on pins 10-17
 145                  */
 146                 compatible = "ti,tca6416";
 147                 reg = <0x20>;
 148                 gpio-controller;
 149                 #gpio-cells = <2>;
 150                 /*
 151                  * IRQ not connected
 152                  * Lines:
 153                  * 0 - PS_GTR_LAN_SEL0
 154                  * 1 - PS_GTR_LAN_SEL1
 155                  * 2 - PS_GTR_LAN_SEL2
 156                  * 3 - PS_GTR_LAN_SEL3
 157                  * 4 - PCI_CLK_DIR_SEL
 158                  * 5 - IIC_MUX_RESET_B
 159                  * 6 - GEM3_EXP_RESET_B
 160                  * 7, 10 - 17 - not connected
 161                  */
 162
 163                 gtr_sel0 {
 164                         gpio-hog;
 165                         gpios = <0 0>;
 166                         output-high; /* PCIE = 0, DP = 1 */
 167                         line-name = "sel0";
 168                 };
 169                 gtr_sel1 {
 170                         gpio-hog;
 171                         gpios = <1 0>;
 172                         output-high; /* PCIE = 0, DP = 1 */
 173                         line-name = "sel1";
 174                 };
 175                 gtr_sel2 {
 176                         gpio-hog;
 177                         gpios = <2 0>;
 178                         output-high; /* PCIE = 0, USB0 = 1 */
 179                         line-name = "sel2";
 180                 };
 181                 gtr_sel3 {
 182                         gpio-hog;
 183                         gpios = <3 0>;
 184                         output-high; /* PCIE = 0, SATA = 1 */
 185                         line-name = "sel3";
 186                 };
 187         };
 188
 189         tca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */
 190                 compatible = "ti,tca6416";
 191                 reg = <0x21>;
 192                 gpio-controller;
 193                 #gpio-cells = <2>;
 194                 /*
 195                  * IRQ not connected
 196                  * Lines:
 197                  * 0 - VCCPSPLL_EN
 198                  * 1 - MGTRAVCC_EN
 199                  * 2 - MGTRAVTT_EN
 200                  * 3 - VCCPSDDRPLL_EN
 201                  * 4 - MIO26_PMU_INPUT_LS
 202                  * 5 - PL_PMBUS_ALERT
 203                  * 6 - PS_PMBUS_ALERT
 204                  * 7 - MAXIM_PMBUS_ALERT
 205                  * 10 - PL_DDR4_VTERM_EN
 206                  * 11 - PL_DDR4_VPP_2V5_EN
 207                  * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON
 208                  * 13 - PS_DIMM_SUSPEND_EN
 209                  * 14 - PS_DDR4_VTERM_EN
 210                  * 15 - PS_DDR4_VPP_2V5_EN
 211                  * 16 - 17 - not connected
 212                  */
 213         };
 214
 215         i2cswitch@75 { /* u60 */
 216                 compatible = "nxp,pca9544";
 217                 #address-cells = <1>;
 218                 #size-cells = <0>;
 219                 reg = <0x75>;
 220                 i2c@0 { /* i2c mw 75 0 1 */
 221                         #address-cells = <1>;
 222                         #size-cells = <0>;
 223                         reg = <0>;
 224                         /* PS_PMBUS */
 225                         ina226@40 { /* u76 */
 226                                 compatible = "ti,ina226";
 227                                 reg = <0x40>;
 228                                 shunt-resistor = <5000>;
 229                         };
 230                         ina226@41 { /* u77 */
 231                                 compatible = "ti,ina226";
 232                                 reg = <0x41>;
 233                                 shunt-resistor = <5000>;
 234                         };
 235                         ina226@42 { /* u78 */
 236                                 compatible = "ti,ina226";
 237                                 reg = <0x42>;
 238                                 shunt-resistor = <5000>;
 239                         };
 240                         ina226@43 { /* u87 */
 241                                 compatible = "ti,ina226";
 242                                 reg = <0x43>;
 243                                 shunt-resistor = <5000>;
 244                         };
 245                         ina226@44 { /* u85 */
 246                                 compatible = "ti,ina226";
 247                                 reg = <0x44>;
 248                                 shunt-resistor = <5000>;
 249                         };
 250                         ina226@45 { /* u86 */
 251                                 compatible = "ti,ina226";
 252                                 reg = <0x45>;
 253                                 shunt-resistor = <5000>;
 254                         };
 255                         ina226@46 { /* u93 */
 256                                 compatible = "ti,ina226";
 257                                 reg = <0x46>;
 258                                 shunt-resistor = <5000>;
 259                         };
 260                         ina226@47 { /* u88 */
 261                                 compatible = "ti,ina226";
 262                                 reg = <0x47>;
 263                                 shunt-resistor = <5000>;
 264                         };
 265                         ina226@4a { /* u15 */
 266                                 compatible = "ti,ina226";
 267                                 reg = <0x4a>;
 268                                 shunt-resistor = <5000>;
 269                         };
 270                         ina226@4b { /* u92 */
 271                                 compatible = "ti,ina226";
 272                                 reg = <0x4b>;
 273                                 shunt-resistor = <5000>;
 274                         };
 275                 };
 276                 i2c@1 { /* i2c mw 75 0 1 */
 277                         #address-cells = <1>;
 278                         #size-cells = <0>;
 279                         reg = <1>;
 280                         /* PL_PMBUS */
 281                         ina226@40 { /* u79 */
 282                                 compatible = "ti,ina226";
 283                                 reg = <0x40>;
 284                                 shunt-resistor = <2000>;
 285                         };
 286                         ina226@41 { /* u81 */
 287                                 compatible = "ti,ina226";
 288                                 reg = <0x41>;
 289                                 shunt-resistor = <5000>;
 290                         };
 291                         ina226@42 { /* u80 */
 292                                 compatible = "ti,ina226";
 293                                 reg = <0x42>;
 294                                 shunt-resistor = <5000>;
 295                         };
 296                         ina226@43 { /* u84 */
 297                                 compatible = "ti,ina226";
 298                                 reg = <0x43>;
 299                                 shunt-resistor = <5000>;
 300                         };
 301                         ina226@44 { /* u16 */
 302                                 compatible = "ti,ina226";
 303                                 reg = <0x44>;
 304                                 shunt-resistor = <5000>;
 305                         };
 306                         ina226@45 { /* u65 */
 307                                 compatible = "ti,ina226";
 308                                 reg = <0x45>;
 309                                 shunt-resistor = <5000>;
 310                         };
 311                         ina226@46 { /* u74 */
 312                                 compatible = "ti,ina226";
 313                                 reg = <0x46>;
 314                                 shunt-resistor = <5000>;
 315                         };
 316                         ina226@47 { /* u75 */
 317                                 compatible = "ti,ina226";
 318                                 reg = <0x47>;
 319                                 shunt-resistor = <5000>;
 320                         };
 321                 };
 322                 i2c@2 { /* i2c mw 75 0 1 */
 323                         #address-cells = <1>;
 324                         #size-cells = <0>;
 325                         reg = <2>;
 326                         /* MAXIM_PMBUS - 00 */
 327                         max15301@a { /* u46 */
 328                                 compatible = "max15301";
 329                                 reg = <0xa>;
 330                         };
 331                         max15303@b { /* u4 */
 332                                 compatible = "max15303";
 333                                 reg = <0xb>;
 334                         };
 335                         max15303@10 { /* u13 */
 336                                 compatible = "max15303";
 337                                 reg = <0x10>;
 338                         };
 339                         max15301@13 { /* u47 */
 340                                 compatible = "max15301";
 341                                 reg = <0x13>;
 342                         };
 343                         max15303@14 { /* u7 */
 344                                 compatible = "max15303";
 345                                 reg = <0x14>;
 346                         };
 347                         max15303@15 { /* u6 */
 348                                 compatible = "max15303";
 349                                 reg = <0x15>;
 350                         };
 351                         max15303@16 { /* u10 */
 352                                 compatible = "max15303";
 353                                 reg = <0x16>;
 354                         };
 355                         max15303@17 { /* u9 */
 356                                 compatible = "max15303";
 357                                 reg = <0x17>;
 358                         };
 359                         max15301@18 { /* u63 */
 360                                 compatible = "max15301";
 361                                 reg = <0x18>;
 362                         };
 363                         max15303@1a { /* u49 */
 364                                 compatible = "max15303";
 365                                 reg = <0x1a>;
 366                         };
 367                         max15303@1d { /* u18 */
 368                                 compatible = "max15303";
 369                                 reg = <0x1d>;
 370                         };
 371                         max15303@20 { /* u8 */
 372                                 compatible = "max15303";
 373                                 status = "disabled"; /* unreachable */
 374                                 reg = <0x20>;
 375                         };
 376
 377 /*                      drivers/hwmon/pmbus/Kconfig:86:   be called max20751.
 378 drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751)  += max20751.o
 379 */
 380                         max20751@72 { /* u95 FIXME - not detected */
 381                                 compatible = "max20751";
 382                                 reg = <0x72>;
 383                         };
 384                         max20751@73 { /* u96 FIXME - not detected */
 385                                 compatible = "max20751";
 386                                 reg = <0x73>;
 387                         };
 388                 };
 389                 /* Bus 3 is not connected */
 390         };
 391
 392         /* FIXME PL connection - u55 , PMOD - j160 */
 393         /* FIXME MSP430F - u41 - not detected */
 394 };
 395
 396 &i2c1 {
 397         status = "okay";
 398         clock-frequency = <400000>;
 399         /* FIXME PL i2c via PCA9306 - u45 */
 400         /* FIXME MSP430 - u41 - not detected */
 401         i2cswitch@74 { /* u34 */
 402                 compatible = "nxp,pca9548";
 403                 #address-cells = <1>;
 404                 #size-cells = <0>;
 405                 reg = <0x74>;
 406                 i2c@0 { /* i2c mw 74 0 1 */
 407                         #address-cells = <1>;
 408                         #size-cells = <0>;
 409                         reg = <0>;
 410                         /*
 411                          * IIC_EEPROM 1kB memory which uses 256B blocks
 412                          * where every block has different address.
 413                          *    0 - 256B address 0x54
 414                          * 256B - 512B address 0x55
 415                          * 512B - 768B address 0x56
 416                          * 768B - 1024B address 0x57
 417                          */
 418                         eeprom@54 { /* u23 */
 419                                 compatible = "at,24c08";
 420                                 reg = <0x54>;
 421                         };
 422                 };
 423                 i2c@1 { /* i2c mw 74 0 2 */
 424                         #address-cells = <1>;
 425                         #size-cells = <0>;
 426                         reg = <1>;
 427                         si5341: clock-generator1@36 { /* SI5341 - u69 */
 428                                 compatible = "si5341";
 429                                 reg = <0x36>;
 430                         };
 431
 432                 };
 433                 i2c@2 { /* i2c mw 74 0 4 */
 434                         #address-cells = <1>;
 435                         #size-cells = <0>;
 436                         reg = <2>;
 437                         si570_1: clock-generator2@5d { /* USER SI570 - u42 */
 438                                 #clock-cells = <0>;
 439                                 compatible = "silabs,si570";
 440                                 reg = <0x5d>;
 441                                 temperature-stability = <50>;
 442                                 factory-fout = <300000000>;
 443                                 clock-frequency = <300000000>;
 444                         };
 445                 };
 446                 i2c@3 { /* i2c mw 74 0 8 */
 447                         #address-cells = <1>;
 448                         #size-cells = <0>;
 449                         reg = <3>;
 450                         si570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */
 451                                 #clock-cells = <0>;
 452                                 compatible = "silabs,si570";
 453                                 reg = <0x5d>;
 454                                 temperature-stability = <50>; /* copy from zc702 */
 455                                 factory-fout = <156250000>;
 456                                 clock-frequency = <148500000>;
 457                         };
 458                 };
 459                 i2c@4 { /* i2c mw 74 0 10 */
 460                         #address-cells = <1>;
 461                         #size-cells = <0>;
 462                         reg = <4>;
 463                         si5328: clock-generator4@69 {/* SI5328 - u20 */
 464                                 compatible = "silabs,si5328";
 465                                 reg = <0x69>;
 466                         };
 467                 };
 468                 /* 5 - 7 unconnected */
 469         };
 470
 471         i2cswitch@75 {
 472                 compatible = "nxp,pca9548"; /* u135 */
 473                 #address-cells = <1>;
 474                 #size-cells = <0>;
 475                 reg = <0x75>;
 476
 477                 i2c@0 {
 478                         #address-cells = <1>;
 479                         #size-cells = <0>;
 480                         reg = <0>;
 481                         /* HPC0_IIC */
 482                 };
 483                 i2c@1 {
 484                         #address-cells = <1>;
 485                         #size-cells = <0>;
 486                         reg = <1>;
 487                         /* HPC1_IIC */
 488                 };
 489                 i2c@2 {
 490                         #address-cells = <1>;
 491                         #size-cells = <0>;
 492                         reg = <2>;
 493                         /* SYSMON */
 494                 };
 495                 i2c@3 { /* i2c mw 75 0 8 */
 496                         #address-cells = <1>;
 497                         #size-cells = <0>;
 498                         reg = <3>;
 499                         /* DDR4 SODIMM */
 500                         dev@19 { /* u-boot detection */
 501                                 compatible = "xxx";
 502                                 reg = <0x19>;
 503                         };
 504                         dev@30 { /* u-boot detection */
 505                                 compatible = "xxx";
 506                                 reg = <0x30>;
 507                         };
 508                         dev@35 { /* u-boot detection */
 509                                 compatible = "xxx";
 510                                 reg = <0x35>;
 511                         };
 512                         dev@36 { /* u-boot detection */
 513                                 compatible = "xxx";
 514                                 reg = <0x36>;
 515                         };
 516                         dev@51 { /* u-boot detection - maybe SPD */
 517                                 compatible = "xxx";
 518                                 reg = <0x51>;
 519                         };
 520                 };
 521                 i2c@4 {
 522                         #address-cells = <1>;
 523                         #size-cells = <0>;
 524                         reg = <4>;
 525                         /* SEP 3 */
 526                 };
 527                 i2c@5 {
 528                         #address-cells = <1>;
 529                         #size-cells = <0>;
 530                         reg = <5>;
 531                         /* SEP 2 */
 532                 };
 533                 i2c@6 {
 534                         #address-cells = <1>;
 535                         #size-cells = <0>;
 536                         reg = <6>;
 537                         /* SEP 1 */
 538                 };
 539                 i2c@7 {
 540                         #address-cells = <1>;
 541                         #size-cells = <0>;
 542                         reg = <7>;
 543                         /* SEP 0 */
 544                 };
 545         };
 546 };
 547
 548 &pcie {
 549 /*      status = "okay"; */
 550 };
 551
 552 &qspi {
 553         status = "okay";
 554         is-dual = <1>;
 555         flash@0 {
 556                 compatible = "m25p80"; /* 32MB */
 557                 #address-cells = <1>;
 558                 #size-cells = <1>;
 559                 reg = <0x0>;
 560                 spi-tx-bus-width = <1>;
 561                 spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
 562                 spi-max-frequency = <108000000>; /* Based on DC1 spec */
 563                 partition@qspi-fsbl-uboot { /* for testing purpose */
 564                         label = "qspi-fsbl-uboot";
 565                         reg = <0x0 0x100000>;
 566                 };
 567                 partition@qspi-linux { /* for testing purpose */
 568                         label = "qspi-linux";
 569                         reg = <0x100000 0x500000>;
 570                 };
 571                 partition@qspi-device-tree { /* for testing purpose */
 572                         label = "qspi-device-tree";
 573                         reg = <0x600000 0x20000>;
 574                 };
 575                 partition@qspi-rootfs { /* for testing purpose */
 576                         label = "qspi-rootfs";
 577                         reg = <0x620000 0x5E0000>;
 578                 };
 579         };
 580 };
 581
 582 &rtc {
 583         status = "okay";
 584 };
 585
 586 &sata {
 587         status = "okay";
 588         /* SATA OOB timing settings */
 589         ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
 590         ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
 591         ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
 592         ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
 593         ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
 594         ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
 595         ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
 596         ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
 597 };
 598
 599 /* SD1 with level shifter */
 600 &sdhci1 {
 601         status = "okay";
 602         no-1-8-v;       /* for 1.0 silicon */
 603 };
 604
 605 &uart0 {
 606         status = "okay";
 607 };
 608
 609 &uart1 {
 610         status = "okay";
 611 };
 612
 613 /* ULPI SMSC USB3320 */
 614 &usb0 {
 615         status = "okay";
 616 };
 617
 618 &dwc3_0 {
 619         status = "okay";
 620         dr_mode = "host";
 621 };
 622
 623 &xilinx_drm {
 624         status = "okay";
 625         clocks = <&si570_1>;
 626 };
 627
 628 &xlnx_dp {
 629         status = "okay";
 630 };
 631
 632 &xlnx_dp_sub {
 633         status = "okay";
 634         xlnx,vid-clk-pl;
 635 };
 636
 637 &xlnx_dp_snd_pcm0 {
 638         status = "okay";
 639 };
 640
 641 &xlnx_dp_snd_pcm1 {
 642         status = "okay";
 643 };
 644
 645 &xlnx_dp_snd_card {
 646         status = "okay";
 647 };
 648
 649 &xlnx_dp_snd_codec0 {
 650         status = "okay";
 651 };
 652
 653 &xlnx_dpdma {
 654         status = "okay";
 655 };