1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP ZCU111
5 * (C) Copyright 2017 - 2018, Xilinx, Inc.
7 * Michal Simek <michal.simek@xilinx.com>
12 #include "zynqmp.dtsi"
13 #include "zynqmp-clk-ccf.dtsi"
14 #include <dt-bindings/input/input.h>
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/phy/phy.h>
19 model = "ZynqMP ZCU111 RevA";
20 compatible = "xlnx,zynqmp-zcu111-revA", "xlnx,zynqmp-zcu111", "xlnx,zynqmp";
36 bootargs = "earlycon";
37 stdout-path = "serial0:115200n8";
41 device_type = "memory";
42 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
43 /* Another 4GB connected to PL */
47 compatible = "gpio-keys";
53 gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
54 linux,code = <KEY_DOWN>;
61 compatible = "gpio-leds";
64 gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
65 linux,default-trigger = "heartbeat";
108 phy-handle = <&phy0>;
109 phy-mode = "rgmii-id";
112 ti,rx-internal-delay = <0x8>;
113 ti,tx-internal-delay = <0xa>;
114 ti,fifo-depth = <0x1>;
128 clock-frequency = <400000>;
130 tca6416_u22: gpio@20 {
131 compatible = "ti,tca6416";
133 gpio-controller; /* interrupt not connected */
139 * 1 - MAX6643_FANFAIL_B
140 * 2 - MIO26_PMU_INPUT_LS
141 * 4 - SFP_SI5382_INT_ALM
142 * 5 - IIC_MUX_RESET_B
143 * 6 - GEM3_EXP_RESET_B
144 * 10 - FMCP_HSPC_PRSNT_M2C_B
145 * 11 - CLK_SPI_MUX_SEL0
146 * 12 - CLK_SPI_MUX_SEL1
147 * 16 - IRPS5401_ALERT_B
148 * 17 - INA226_PMBUS_ALERT
149 * 3, 7, 13-15 - not connected
153 i2c-mux@75 { /* u23 */
154 compatible = "nxp,pca9544";
155 #address-cells = <1>;
159 #address-cells = <1>;
163 /* PMBUS_ALERT done via pca9544 */
164 ina226@40 { /* u67 */
165 compatible = "ti,ina226";
167 shunt-resistor = <2000>;
169 ina226@41 { /* u59 */
170 compatible = "ti,ina226";
172 shunt-resistor = <5000>;
174 ina226@42 { /* u61 */
175 compatible = "ti,ina226";
177 shunt-resistor = <5000>;
179 ina226@43 { /* u60 */
180 compatible = "ti,ina226";
182 shunt-resistor = <5000>;
184 ina226@45 { /* u64 */
185 compatible = "ti,ina226";
187 shunt-resistor = <5000>;
189 ina226@46 { /* u69 */
190 compatible = "ti,ina226";
192 shunt-resistor = <2000>;
194 ina226@47 { /* u66 */
195 compatible = "ti,ina226";
197 shunt-resistor = <5000>;
199 ina226@48 { /* u65 */
200 compatible = "ti,ina226";
202 shunt-resistor = <5000>;
204 ina226@49 { /* u63 */
205 compatible = "ti,ina226";
207 shunt-resistor = <5000>;
210 compatible = "ti,ina226";
212 shunt-resistor = <5000>;
214 ina226@4b { /* u71 */
215 compatible = "ti,ina226";
217 shunt-resistor = <5000>;
219 ina226@4c { /* u77 */
220 compatible = "ti,ina226";
222 shunt-resistor = <5000>;
224 ina226@4d { /* u73 */
225 compatible = "ti,ina226";
227 shunt-resistor = <5000>;
229 ina226@4e { /* u79 */
230 compatible = "ti,ina226";
232 shunt-resistor = <5000>;
236 #address-cells = <1>;
242 #address-cells = <1>;
245 irps5401_43: irps54012@43 { /* IRPS5401 - u53 check these */
247 compatible = "infineon,irps5401";
250 irps5401_44: irps54012@44 { /* IRPS5401 - u55 */
252 compatible = "infineon,irps5401";
255 irps5401_45: irps54012@45 { /* IRPS5401 - u57 */
257 compatible = "infineon,irps5401";
268 #address-cells = <1>;
278 clock-frequency = <400000>;
280 i2c-mux@74 { /* u26 */
281 compatible = "nxp,pca9548";
282 #address-cells = <1>;
286 #address-cells = <1>;
290 * IIC_EEPROM 1kB memory which uses 256B blocks
291 * where every block has different address.
292 * 0 - 256B address 0x54
293 * 256B - 512B address 0x55
294 * 512B - 768B address 0x56
295 * 768B - 1024B address 0x57
297 eeprom: eeprom@54 { /* u88 */
298 compatible = "atmel,24c08";
303 #address-cells = <1>;
306 si5341: clock-generator@36 { /* SI5341 - u46 */
307 compatible = "si5341";
313 #address-cells = <1>;
316 si570_1: clock-generator@5d { /* USER SI570 - u47 */
318 compatible = "silabs,si570";
320 temperature-stability = <50>;
321 factory-fout = <300000000>;
322 clock-frequency = <300000000>;
326 #address-cells = <1>;
329 si570_2: clock-generator@5d { /* USER MGT SI570 - u49 */
331 compatible = "silabs,si570";
333 temperature-stability = <50>;
334 factory-fout = <156250000>;
335 clock-frequency = <148500000>;
339 #address-cells = <1>;
342 si5328: clock-generator@69 { /* SI5328 - u48 */
343 compatible = "silabs,si5328";
348 #address-cells = <1>;
351 sc18is603@2f { /* sc18is602 - u93 */
352 compatible = "nxp,sc18is603";
354 /* 4 gpios for CS not handled by driver */
365 #address-cells = <1>;
374 compatible = "nxp,pca9548"; /* u27 */
375 #address-cells = <1>;
380 #address-cells = <1>;
386 #address-cells = <1>;
392 #address-cells = <1>;
398 #address-cells = <1>;
402 dev@19 { /* u-boot detection FIXME */
406 dev@30 { /* u-boot detection */
410 dev@35 { /* u-boot detection */
414 dev@36 { /* u-boot detection */
418 dev@51 { /* u-boot detection - maybe SPD */
424 #address-cells = <1>;
430 #address-cells = <1>;
436 #address-cells = <1>;
442 #address-cells = <1>;
454 compatible = "m25p80"; /* 32MB */
455 #address-cells = <1>;
458 spi-tx-bus-width = <1>;
459 spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
460 spi-max-frequency = <108000000>; /* Based on DC1 spec */
461 partition@qspi-fsbl-uboot { /* for testing purpose */
462 label = "qspi-fsbl-uboot";
463 reg = <0x0 0x100000>;
465 partition@qspi-linux { /* for testing purpose */
466 label = "qspi-linux";
467 reg = <0x100000 0x500000>;
469 partition@qspi-device-tree { /* for testing purpose */
470 label = "qspi-device-tree";
471 reg = <0x600000 0x20000>;
473 partition@qspi-rootfs { /* for testing purpose */
474 label = "qspi-rootfs";
475 reg = <0x620000 0x5E0000>;
486 /* SATA OOB timing settings */
487 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
488 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
489 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
490 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
491 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
492 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
493 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
494 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
495 phy-names = "sata-phy";
496 phys = <&lane3 PHY_TYPE_SATA 1 3 125000000>;
499 /* SD1 with level shifter */
515 /* ULPI SMSC USB3320 */
523 snps,usb3_lpm_capable;
524 phy-names = "usb3-phy";
525 phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;