2 * dts file for Xilinx ZynqMP
4 * (C) Copyright 2014 - 2015, Xilinx, Inc.
6 * Michal Simek <michal.simek@xilinx.com>
8 * SPDX-License-Identifier: GPL-2.0+
11 compatible = "xlnx,zynqmp";
20 compatible = "arm,cortex-a53", "arm,armv8";
22 enable-method = "psci";
27 compatible = "arm,cortex-a53", "arm,armv8";
29 enable-method = "psci";
34 compatible = "arm,cortex-a53", "arm,armv8";
36 enable-method = "psci";
41 compatible = "arm,cortex-a53", "arm,armv8";
43 enable-method = "psci";
49 compatible = "arm,dcc";
55 compatible = "xlnx,zynqmp-genpd";
58 #power-domain-cells = <0x0>;
63 #power-domain-cells = <0x0>;
68 #power-domain-cells = <0x0>;
73 #power-domain-cells = <0x0>;
78 #power-domain-cells = <0x0>;
83 #power-domain-cells = <0x0>;
88 #power-domain-cells = <0x0>;
93 #power-domain-cells = <0x0>;
98 #power-domain-cells = <0x0>;
103 #power-domain-cells = <0x0>;
108 #power-domain-cells = <0x0>;
113 #power-domain-cells = <0x0>;
118 #power-domain-cells = <0x0>;
123 /* fixme: what to attach to */
124 #power-domain-cells = <0x0>;
129 #power-domain-cells = <0x0>;
134 #power-domain-cells = <0x0>;
139 #power-domain-cells = <0x0>;
144 #power-domain-cells = <0x0>;
149 #power-domain-cells = <0x0>;
154 #power-domain-cells = <0x0>;
159 #power-domain-cells = <0x0>;
164 #power-domain-cells = <0x0>;
169 #power-domain-cells = <0x0>;
174 #power-domain-cells = <0x0>;
179 #power-domain-cells = <0x0>;
184 #power-domain-cells = <0x0>;
189 #power-domain-cells = <0x0>;
194 #power-domain-cells = <0x0>;
199 #power-domain-cells = <0x0>;
200 pd-id = <0x3a 0x14 0x15>;
205 compatible = "arm,armv8-pmuv3";
206 interrupt-parent = <&gic>;
207 interrupts = <0 143 4>,
214 compatible = "arm,psci-0.2";
219 compatible = "xlnx,zynqmp-pm";
224 compatible = "arm,armv8-timer";
225 interrupt-parent = <&gic>;
226 interrupts = <1 13 0xf01>,
233 compatible = "arm,cortex-a53-edac";
237 compatible = "xlnx,zynqmp-pcap-fpga";
240 amba_apu: amba_apu@0 {
241 compatible = "simple-bus";
242 #address-cells = <2>;
244 ranges = <0 0 0 0 0xffffffff>;
246 gic: interrupt-controller@f9010000 {
247 compatible = "arm,gic-400", "arm,cortex-a15-gic";
248 #interrupt-cells = <3>;
249 reg = <0x0 0xf9010000 0x10000>,
250 <0x0 0xf9020000 0x20000>,
251 <0x0 0xf9040000 0x20000>,
252 <0x0 0xf9060000 0x20000>;
253 interrupt-controller;
254 interrupt-parent = <&gic>;
255 interrupts = <1 9 0xf04>;
260 compatible = "simple-bus";
262 #address-cells = <2>;
267 compatible = "xlnx,zynq-can-1.0";
269 clock-names = "can_clk", "pclk";
270 reg = <0x0 0xff060000 0x0 0x1000>;
271 interrupts = <0 23 4>;
272 interrupt-parent = <&gic>;
273 tx-fifo-depth = <0x40>;
274 rx-fifo-depth = <0x40>;
275 power-domains = <&pd_can0>;
279 compatible = "xlnx,zynq-can-1.0";
281 clock-names = "can_clk", "pclk";
282 reg = <0x0 0xff070000 0x0 0x1000>;
283 interrupts = <0 24 4>;
284 interrupt-parent = <&gic>;
285 tx-fifo-depth = <0x40>;
286 rx-fifo-depth = <0x40>;
287 power-domains = <&pd_can1>;
291 compatible = "arm,cci-400";
292 reg = <0x0 0xfd6e0000 0x0 0x9000>;
293 ranges = <0x0 0x0 0xfd6e0000 0x10000>;
294 #address-cells = <1>;
298 compatible = "arm,cci-400-pmu,r1";
299 reg = <0x9000 0x5000>;
300 interrupt-parent = <&gic>;
301 interrupts = <0 123 4>,
310 fpd_dma_chan1: dma@fd500000 {
312 compatible = "xlnx,zynqmp-dma-1.0";
313 reg = <0x0 0xfd500000 0x0 0x1000>;
314 interrupt-parent = <&gic>;
315 interrupts = <0 124 4>;
316 clock-names = "clk_main", "clk_apb";
317 xlnx,bus-width = <128>;
318 #stream-id-cells = <1>;
319 iommus = <&smmu 0x14e8>;
320 power-domains = <&pd_gdma>;
323 fpd_dma_chan2: dma@fd510000 {
325 compatible = "xlnx,zynqmp-dma-1.0";
326 reg = <0x0 0xfd510000 0x0 0x1000>;
327 interrupt-parent = <&gic>;
328 interrupts = <0 125 4>;
329 clock-names = "clk_main", "clk_apb";
330 xlnx,bus-width = <128>;
331 #stream-id-cells = <1>;
332 iommus = <&smmu 0x14e9>;
333 power-domains = <&pd_gdma>;
336 fpd_dma_chan3: dma@fd520000 {
338 compatible = "xlnx,zynqmp-dma-1.0";
339 reg = <0x0 0xfd520000 0x0 0x1000>;
340 interrupt-parent = <&gic>;
341 interrupts = <0 126 4>;
342 clock-names = "clk_main", "clk_apb";
343 xlnx,bus-width = <128>;
344 #stream-id-cells = <1>;
345 iommus = <&smmu 0x14ea>;
346 power-domains = <&pd_gdma>;
349 fpd_dma_chan4: dma@fd530000 {
351 compatible = "xlnx,zynqmp-dma-1.0";
352 reg = <0x0 0xfd530000 0x0 0x1000>;
353 interrupt-parent = <&gic>;
354 interrupts = <0 127 4>;
355 clock-names = "clk_main", "clk_apb";
356 xlnx,bus-width = <128>;
357 #stream-id-cells = <1>;
358 iommus = <&smmu 0x14eb>;
359 power-domains = <&pd_gdma>;
362 fpd_dma_chan5: dma@fd540000 {
364 compatible = "xlnx,zynqmp-dma-1.0";
365 reg = <0x0 0xfd540000 0x0 0x1000>;
366 interrupt-parent = <&gic>;
367 interrupts = <0 128 4>;
368 clock-names = "clk_main", "clk_apb";
369 xlnx,bus-width = <128>;
370 #stream-id-cells = <1>;
371 iommus = <&smmu 0x14ec>;
372 power-domains = <&pd_gdma>;
375 fpd_dma_chan6: dma@fd550000 {
377 compatible = "xlnx,zynqmp-dma-1.0";
378 reg = <0x0 0xfd550000 0x0 0x1000>;
379 interrupt-parent = <&gic>;
380 interrupts = <0 129 4>;
381 clock-names = "clk_main", "clk_apb";
382 xlnx,bus-width = <128>;
383 #stream-id-cells = <1>;
384 iommus = <&smmu 0x14ed>;
385 power-domains = <&pd_gdma>;
388 fpd_dma_chan7: dma@fd560000 {
390 compatible = "xlnx,zynqmp-dma-1.0";
391 reg = <0x0 0xfd560000 0x0 0x1000>;
392 interrupt-parent = <&gic>;
393 interrupts = <0 130 4>;
394 clock-names = "clk_main", "clk_apb";
395 xlnx,bus-width = <128>;
396 #stream-id-cells = <1>;
397 iommus = <&smmu 0x14ee>;
398 power-domains = <&pd_gdma>;
401 fpd_dma_chan8: dma@fd570000 {
403 compatible = "xlnx,zynqmp-dma-1.0";
404 reg = <0x0 0xfd570000 0x0 0x1000>;
405 interrupt-parent = <&gic>;
406 interrupts = <0 131 4>;
407 clock-names = "clk_main", "clk_apb";
408 xlnx,bus-width = <128>;
409 #stream-id-cells = <1>;
410 iommus = <&smmu 0x14ef>;
411 power-domains = <&pd_gdma>;
416 compatible = "arm,mali-400", "arm,mali-utgard";
417 reg = <0x0 0xfd4b0000 0x0 0x30000>;
418 interrupt-parent = <&gic>;
419 interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>;
420 interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1";
421 power-domains = <&pd_gpu>;
424 /* LPDDMA default allows only secured access. inorder to enable
425 * These dma channels, Users should ensure that these dma
426 * Channels are allowed for non secure access.
428 lpd_dma_chan1: dma@ffa80000 {
430 compatible = "xlnx,zynqmp-dma-1.0";
431 clock-names = "clk_main", "clk_apb";
432 reg = <0x0 0xffa80000 0x0 0x1000>;
433 interrupt-parent = <&gic>;
434 interrupts = <0 77 4>;
435 xlnx,bus-width = <64>;
436 #stream-id-cells = <1>;
437 iommus = <&smmu 0x868>;
438 power-domains = <&pd_adma>;
441 lpd_dma_chan2: dma@ffa90000 {
443 compatible = "xlnx,zynqmp-dma-1.0";
444 clock-names = "clk_main", "clk_apb";
445 reg = <0x0 0xffa90000 0x0 0x1000>;
446 interrupt-parent = <&gic>;
447 interrupts = <0 78 4>;
448 xlnx,bus-width = <64>;
449 #stream-id-cells = <1>;
450 iommus = <&smmu 0x869>;
451 power-domains = <&pd_adma>;
454 lpd_dma_chan3: dma@ffaa0000 {
456 compatible = "xlnx,zynqmp-dma-1.0";
457 clock-names = "clk_main", "clk_apb";
458 reg = <0x0 0xffaa0000 0x0 0x1000>;
459 interrupt-parent = <&gic>;
460 interrupts = <0 79 4>;
461 xlnx,bus-width = <64>;
462 #stream-id-cells = <1>;
463 iommus = <&smmu 0x86a>;
464 power-domains = <&pd_adma>;
467 lpd_dma_chan4: dma@ffab0000 {
469 compatible = "xlnx,zynqmp-dma-1.0";
470 clock-names = "clk_main", "clk_apb";
471 reg = <0x0 0xffab0000 0x0 0x1000>;
472 interrupt-parent = <&gic>;
473 interrupts = <0 80 4>;
474 xlnx,bus-width = <64>;
475 #stream-id-cells = <1>;
476 iommus = <&smmu 0x86b>;
477 power-domains = <&pd_adma>;
480 lpd_dma_chan5: dma@ffac0000 {
482 compatible = "xlnx,zynqmp-dma-1.0";
483 clock-names = "clk_main", "clk_apb";
484 reg = <0x0 0xffac0000 0x0 0x1000>;
485 interrupt-parent = <&gic>;
486 interrupts = <0 81 4>;
487 xlnx,bus-width = <64>;
488 #stream-id-cells = <1>;
489 iommus = <&smmu 0x86c>;
490 power-domains = <&pd_adma>;
493 lpd_dma_chan6: dma@ffad0000 {
495 compatible = "xlnx,zynqmp-dma-1.0";
496 clock-names = "clk_main", "clk_apb";
497 reg = <0x0 0xffad0000 0x0 0x1000>;
498 interrupt-parent = <&gic>;
499 interrupts = <0 82 4>;
500 xlnx,bus-width = <64>;
501 #stream-id-cells = <1>;
502 iommus = <&smmu 0x86d>;
503 power-domains = <&pd_adma>;
506 lpd_dma_chan7: dma@ffae0000 {
508 compatible = "xlnx,zynqmp-dma-1.0";
509 clock-names = "clk_main", "clk_apb";
510 reg = <0x0 0xffae0000 0x0 0x1000>;
511 interrupt-parent = <&gic>;
512 interrupts = <0 83 4>;
513 xlnx,bus-width = <64>;
514 #stream-id-cells = <1>;
515 iommus = <&smmu 0x86e>;
516 power-domains = <&pd_adma>;
519 lpd_dma_chan8: dma@ffaf0000 {
521 compatible = "xlnx,zynqmp-dma-1.0";
522 clock-names = "clk_main", "clk_apb";
523 reg = <0x0 0xffaf0000 0x0 0x1000>;
524 interrupt-parent = <&gic>;
525 interrupts = <0 84 4>;
526 xlnx,bus-width = <64>;
527 #stream-id-cells = <1>;
528 iommus = <&smmu 0x86f>;
529 power-domains = <&pd_adma>;
532 mc: memory-controller@fd070000 {
533 compatible = "xlnx,zynqmp-ddrc-2.40a";
534 reg = <0x0 0xfd070000 0x0 0x30000>;
535 interrupt-parent = <&gic>;
536 interrupts = <0 112 4>;
539 nand0: nand@ff100000 {
540 compatible = "arasan,nfc-v3p10";
542 reg = <0x0 0xff100000 0x0 0x1000>;
543 clock-names = "clk_sys", "clk_flash";
544 interrupt-parent = <&gic>;
545 interrupts = <0 14 4>;
546 #address-cells = <2>;
548 #stream-id-cells = <1>;
549 iommus = <&smmu 0x872>;
550 power-domains = <&pd_nand>;
553 gem0: ethernet@ff0b0000 {
554 compatible = "cdns,zynqmp-gem";
556 interrupt-parent = <&gic>;
557 interrupts = <0 57 4>, <0 57 4>;
558 reg = <0x0 0xff0b0000 0x0 0x1000>;
559 clock-names = "pclk", "hclk", "tx_clk";
560 #address-cells = <1>;
562 #stream-id-cells = <1>;
563 iommus = <&smmu 0x874>;
564 power-domains = <&pd_eth0>;
567 gem1: ethernet@ff0c0000 {
568 compatible = "cdns,zynqmp-gem";
570 interrupt-parent = <&gic>;
571 interrupts = <0 59 4>, <0 59 4>;
572 reg = <0x0 0xff0c0000 0x0 0x1000>;
573 clock-names = "pclk", "hclk", "tx_clk";
574 #address-cells = <1>;
576 #stream-id-cells = <1>;
577 iommus = <&smmu 0x875>;
578 power-domains = <&pd_eth1>;
581 gem2: ethernet@ff0d0000 {
582 compatible = "cdns,zynqmp-gem";
584 interrupt-parent = <&gic>;
585 interrupts = <0 61 4>, <0 61 4>;
586 reg = <0x0 0xff0d0000 0x0 0x1000>;
587 clock-names = "pclk", "hclk", "tx_clk";
588 #address-cells = <1>;
590 #stream-id-cells = <1>;
591 iommus = <&smmu 0x876>;
592 power-domains = <&pd_eth2>;
595 gem3: ethernet@ff0e0000 {
596 compatible = "cdns,zynqmp-gem";
598 interrupt-parent = <&gic>;
599 interrupts = <0 63 4>, <0 63 4>;
600 reg = <0x0 0xff0e0000 0x0 0x1000>;
601 clock-names = "pclk", "hclk", "tx_clk";
602 #address-cells = <1>;
604 #stream-id-cells = <1>;
605 iommus = <&smmu 0x877>;
606 power-domains = <&pd_eth3>;
609 gpio: gpio@ff0a0000 {
610 compatible = "xlnx,zynqmp-gpio-1.0";
613 interrupt-parent = <&gic>;
614 interrupts = <0 16 4>;
615 interrupt-controller;
616 #interrupt-cells = <2>;
617 reg = <0x0 0xff0a0000 0x0 0x1000>;
618 power-domains = <&pd_gpio>;
622 compatible = "cdns,i2c-r1p10";
624 interrupt-parent = <&gic>;
625 interrupts = <0 17 4>;
626 reg = <0x0 0xff020000 0x0 0x1000>;
627 #address-cells = <1>;
629 power-domains = <&pd_i2c0>;
633 compatible = "cdns,i2c-r1p10";
635 interrupt-parent = <&gic>;
636 interrupts = <0 18 4>;
637 reg = <0x0 0xff030000 0x0 0x1000>;
638 #address-cells = <1>;
640 power-domains = <&pd_i2c1>;
643 ocm: memory-controller@ff960000 {
644 compatible = "xlnx,zynqmp-ocmc-1.0";
645 reg = <0x0 0xff960000 0x0 0x1000>;
646 interrupt-parent = <&gic>;
647 interrupts = <0 10 4>;
650 pcie: pcie@fd0e0000 {
651 compatible = "xlnx,nwl-pcie-2.11";
653 #address-cells = <3>;
655 #interrupt-cells = <1>;
658 interrupt-parent = <&gic>;
659 interrupts = <0 118 4>,
662 <0 115 4>, /* MSI_1 [63...32] */
663 <0 114 4>; /* MSI_0 [31...0] */
664 interrupt-names = "misc","dummy","intx", "msi1", "msi0";
665 msi-parent = <&pcie>;
666 reg = <0x0 0xfd0e0000 0x0 0x1000>,
667 <0x0 0xfd480000 0x0 0x1000>,
668 <0x80 0x00000000 0x0 0x1000000>;
669 reg-names = "breg", "pcireg", "cfg";
670 ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000 /* non-prefetchable memory */
671 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */
672 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
673 interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
674 <0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
675 <0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
676 <0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
677 power-domains = <&pd_pcie>;
678 pcie_intc: legacy-interrupt-controller {
679 interrupt-controller;
680 #address-cells = <0>;
681 #interrupt-cells = <1>;
686 compatible = "xlnx,zynqmp-qspi-1.0";
688 clock-names = "ref_clk", "pclk";
689 interrupts = <0 15 4>;
690 interrupt-parent = <&gic>;
692 reg = <0x0 0xff0f0000 0x0 0x1000>,
693 <0x0 0xc0000000 0x0 0x8000000>;
694 #address-cells = <1>;
696 #stream-id-cells = <1>;
697 iommus = <&smmu 0x873>;
698 power-domains = <&pd_qspi>;
702 compatible = "xlnx,zynqmp-rtc";
704 reg = <0x0 0xffa60000 0x0 0x100>;
705 interrupt-parent = <&gic>;
706 interrupts = <0 26 4>, <0 27 4>;
707 interrupt-names = "alarm", "sec";
710 serdes: zynqmp_phy@fd400000 {
711 compatible = "xlnx,zynqmp-psgtr";
713 reg = <0x0 0xfd400000 0x0 0x40000>,
714 <0x0 0xfd3d0000 0x0 0x1000>,
715 <0x0 0xfd1a0000 0x0 0x1000>,
716 <0x0 0xff5e0000 0x0 0x1000>;
717 reg-names = "serdes", "siou", "fpd", "lpd";
718 xlnx,tx_termination_fix;
733 sata: ahci@fd0c0000 {
734 compatible = "ceva,ahci-1v84";
736 reg = <0x0 0xfd0c0000 0x0 0x2000>;
737 interrupt-parent = <&gic>;
738 interrupts = <0 133 4>;
739 power-domains = <&pd_sata>;
742 sdhci0: sdhci@ff160000 {
744 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
746 interrupt-parent = <&gic>;
747 interrupts = <0 48 4>;
748 reg = <0x0 0xff160000 0x0 0x1000>;
749 clock-names = "clk_xin", "clk_ahb";
750 xlnx,device_id = <0>;
751 #stream-id-cells = <1>;
752 iommus = <&smmu 0x870>;
753 power-domains = <&pd_sd0>;
756 sdhci1: sdhci@ff170000 {
758 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
760 interrupt-parent = <&gic>;
761 interrupts = <0 49 4>;
762 reg = <0x0 0xff170000 0x0 0x1000>;
763 clock-names = "clk_xin", "clk_ahb";
764 xlnx,device_id = <1>;
765 #stream-id-cells = <1>;
766 iommus = <&smmu 0x871>;
767 power-domains = <&pd_sd1>;
770 smmu: smmu@fd800000 {
771 compatible = "arm,mmu-500";
772 reg = <0x0 0xfd800000 0x0 0x20000>;
774 #global-interrupts = <1>;
775 interrupt-parent = <&gic>;
776 interrupts = <0 155 4>,
777 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
778 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
779 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
780 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>;
781 mmu-masters = < &gem0 0x874
796 &fpd_dma_chan1 0x14e8
797 &fpd_dma_chan2 0x14e9
798 &fpd_dma_chan3 0x14ea
799 &fpd_dma_chan4 0x14eb
800 &fpd_dma_chan5 0x14ec
801 &fpd_dma_chan6 0x14ed
802 &fpd_dma_chan7 0x14ee
803 &fpd_dma_chan8 0x14ef
810 compatible = "cdns,spi-r1p6";
812 interrupt-parent = <&gic>;
813 interrupts = <0 19 4>;
814 reg = <0x0 0xff040000 0x0 0x1000>;
815 clock-names = "ref_clk", "pclk";
816 #address-cells = <1>;
818 power-domains = <&pd_spi0>;
822 compatible = "cdns,spi-r1p6";
824 interrupt-parent = <&gic>;
825 interrupts = <0 20 4>;
826 reg = <0x0 0xff050000 0x0 0x1000>;
827 clock-names = "ref_clk", "pclk";
828 #address-cells = <1>;
830 power-domains = <&pd_spi1>;
833 ttc0: timer@ff110000 {
834 compatible = "cdns,ttc";
836 interrupt-parent = <&gic>;
837 interrupts = <0 36 4>, <0 37 4>, <0 38 4>;
838 reg = <0x0 0xff110000 0x0 0x1000>;
840 power-domains = <&pd_ttc0>;
843 ttc1: timer@ff120000 {
844 compatible = "cdns,ttc";
846 interrupt-parent = <&gic>;
847 interrupts = <0 39 4>, <0 40 4>, <0 41 4>;
848 reg = <0x0 0xff120000 0x0 0x1000>;
850 power-domains = <&pd_ttc1>;
853 ttc2: timer@ff130000 {
854 compatible = "cdns,ttc";
856 interrupt-parent = <&gic>;
857 interrupts = <0 42 4>, <0 43 4>, <0 44 4>;
858 reg = <0x0 0xff130000 0x0 0x1000>;
860 power-domains = <&pd_ttc2>;
863 ttc3: timer@ff140000 {
864 compatible = "cdns,ttc";
866 interrupt-parent = <&gic>;
867 interrupts = <0 45 4>, <0 46 4>, <0 47 4>;
868 reg = <0x0 0xff140000 0x0 0x1000>;
870 power-domains = <&pd_ttc3>;
873 uart0: serial@ff000000 {
875 compatible = "cdns,uart-r1p12", "xlnx,xuartps";
877 interrupt-parent = <&gic>;
878 interrupts = <0 21 4>;
879 reg = <0x0 0xff000000 0x0 0x1000>;
880 clock-names = "uart_clk", "pclk";
881 power-domains = <&pd_uart0>;
884 uart1: serial@ff010000 {
886 compatible = "cdns,uart-r1p12", "xlnx,xuartps";
888 interrupt-parent = <&gic>;
889 interrupts = <0 22 4>;
890 reg = <0x0 0xff010000 0x0 0x1000>;
891 clock-names = "uart_clk", "pclk";
892 power-domains = <&pd_uart1>;
896 #address-cells = <2>;
899 compatible = "xlnx,zynqmp-dwc3";
900 clock-names = "bus_clk", "ref_clk";
901 clocks = <&clk125>, <&clk125>;
902 #stream-id-cells = <1>;
903 iommus = <&smmu 0x860>;
904 power-domains = <&pd_usb0>;
907 dwc3_0: dwc3@fe200000 {
908 compatible = "snps,dwc3";
910 reg = <0x0 0xfe200000 0x0 0x40000>;
911 interrupt-parent = <&gic>;
912 interrupts = <0 65 4>;
913 /* snps,quirk-frame-length-adjustment = <0x20>; */
919 #address-cells = <2>;
922 compatible = "xlnx,zynqmp-dwc3";
923 clock-names = "bus_clk", "ref_clk";
924 clocks = <&clk125>, <&clk125>;
925 #stream-id-cells = <1>;
926 iommus = <&smmu 0x861>;
927 power-domains = <&pd_usb1>;
930 dwc3_1: dwc3@fe300000 {
931 compatible = "snps,dwc3";
933 reg = <0x0 0xfe300000 0x0 0x40000>;
934 interrupt-parent = <&gic>;
935 interrupts = <0 70 4>;
936 /* snps,quirk-frame-length-adjustment = <0x20>; */
941 watchdog0: watchdog@fd4d0000 {
942 compatible = "cdns,wdt-r1p2";
944 interrupt-parent = <&gic>;
945 interrupts = <0 113 1>;
946 reg = <0x0 0xfd4d0000 0x0 0x1000>;
950 xilinx_drm: xilinx_drm {
951 compatible = "xlnx,drm";
953 xlnx,encoder-slave = <&xlnx_dp>;
954 xlnx,connector-type = "DisplayPort";
955 xlnx,dp-sub = <&xlnx_dp_sub>;
957 xlnx,pixel-format = "rgb565";
959 dmas = <&xlnx_dpdma 3>;
963 dmas = <&xlnx_dpdma 0>,
966 dma-names = "dma0", "dma1", "dma2";
971 xlnx_dp: dp@fd4a0000 {
972 compatible = "xlnx,v-dp";
974 reg = <0x0 0xfd4a0000 0x0 0x1000>;
975 interrupts = <0 119 4>;
976 interrupt-parent = <&gic>;
977 clock-names = "aclk", "aud_clk";
978 xlnx,dp-version = "v1.2";
979 xlnx,max-lanes = <2>;
980 xlnx,max-link-rate = <540000>;
983 xlnx,colormetry = "rgb";
985 xlnx,audio-chan = <2>;
986 xlnx,dp-sub = <&xlnx_dp_sub>;
987 xlnx,max-pclock-frequency = <300000>;
990 xlnx_dp_snd_card: dp_snd_card {
991 compatible = "xlnx,dp-snd-card";
993 xlnx,dp-snd-pcm = <&xlnx_dp_snd_pcm0>, <&xlnx_dp_snd_pcm1>;
994 xlnx,dp-snd-codec = <&xlnx_dp_snd_codec0>;
997 xlnx_dp_snd_codec0: dp_snd_codec0 {
998 compatible = "xlnx,dp-snd-codec";
1000 clock-names = "aud_clk";
1003 xlnx_dp_snd_pcm0: dp_snd_pcm0 {
1004 compatible = "xlnx,dp-snd-pcm";
1005 status = "disabled";
1006 dmas = <&xlnx_dpdma 4>;
1010 xlnx_dp_snd_pcm1: dp_snd_pcm1 {
1011 compatible = "xlnx,dp-snd-pcm";
1012 status = "disabled";
1013 dmas = <&xlnx_dpdma 5>;
1017 xlnx_dp_sub: dp_sub@fd4aa000 {
1018 compatible = "xlnx,dp-sub";
1019 status = "disabled";
1020 reg = <0x0 0xfd4aa000 0x0 0x1000>,
1021 <0x0 0xfd4ab000 0x0 0x1000>,
1022 <0x0 0xfd4ac000 0x0 0x1000>;
1023 reg-names = "blend", "av_buf", "aud";
1024 xlnx,output-fmt = "rgb";
1025 xlnx,vid-fmt = "yuyv";
1026 xlnx,gfx-fmt = "rgb565";
1029 xlnx_dpdma: dma@fd4c0000 {
1030 compatible = "xlnx,dpdma";
1031 status = "disabled";
1032 reg = <0x0 0xfd4c0000 0x0 0x1000>;
1033 interrupts = <0 122 4>;
1034 interrupt-parent = <&gic>;
1035 clock-names = "axi_clk";
1039 compatible = "xlnx,video0";
1042 compatible = "xlnx,video1";
1045 compatible = "xlnx,video2";
1047 dma-graphicschannel {
1048 compatible = "xlnx,graphics";
1051 compatible = "xlnx,audio0";
1054 compatible = "xlnx,audio1";