2 * dts file for Xilinx ZynqMP
4 * (C) Copyright 2014 - 2015, Xilinx, Inc.
6 * Michal Simek <michal.simek@xilinx.com>
8 * SPDX-License-Identifier: GPL-2.0+
12 compatible = "xlnx,zynqmp";
21 compatible = "arm,cortex-a53", "arm,armv8";
23 enable-method = "psci";
24 operating-points-v2 = <&cpu_opp_table>;
26 cpu-idle-states = <&CPU_SLEEP_0>;
30 compatible = "arm,cortex-a53", "arm,armv8";
32 enable-method = "psci";
34 operating-points-v2 = <&cpu_opp_table>;
35 cpu-idle-states = <&CPU_SLEEP_0>;
39 compatible = "arm,cortex-a53", "arm,armv8";
41 enable-method = "psci";
43 operating-points-v2 = <&cpu_opp_table>;
44 cpu-idle-states = <&CPU_SLEEP_0>;
48 compatible = "arm,cortex-a53", "arm,armv8";
50 enable-method = "psci";
52 operating-points-v2 = <&cpu_opp_table>;
53 cpu-idle-states = <&CPU_SLEEP_0>;
57 entry-method = "arm,psci";
59 CPU_SLEEP_0: cpu-sleep-0 {
60 compatible = "arm,idle-state";
61 arm,psci-suspend-param = <0x40000000>;
63 entry-latency-us = <300>;
64 exit-latency-us = <600>;
65 min-residency-us = <10000>;
70 cpu_opp_table: cpu_opp_table {
71 compatible = "operating-points-v2";
74 opp-hz = /bits/ 64 <1199999988>;
75 opp-microvolt = <1000000>;
76 clock-latency-ns = <500000>;
79 opp-hz = /bits/ 64 <599999994>;
80 opp-microvolt = <1000000>;
81 clock-latency-ns = <500000>;
84 opp-hz = /bits/ 64 <399999996>;
85 opp-microvolt = <1000000>;
86 clock-latency-ns = <500000>;
89 opp-hz = /bits/ 64 <299999997>;
90 opp-microvolt = <1000000>;
91 clock-latency-ns = <500000>;
96 compatible = "arm,dcc";
102 compatible = "xlnx,zynqmp-genpd";
105 #power-domain-cells = <0x0>;
110 #power-domain-cells = <0x0>;
115 #power-domain-cells = <0x0>;
120 #power-domain-cells = <0x0>;
125 #power-domain-cells = <0x0>;
130 #power-domain-cells = <0x0>;
135 #power-domain-cells = <0x0>;
140 #power-domain-cells = <0x0>;
145 #power-domain-cells = <0x0>;
150 #power-domain-cells = <0x0>;
155 #power-domain-cells = <0x0>;
160 #power-domain-cells = <0x0>;
165 #power-domain-cells = <0x0>;
170 #power-domain-cells = <0x0>;
175 #power-domain-cells = <0x0>;
180 #power-domain-cells = <0x0>;
185 #power-domain-cells = <0x0>;
190 #power-domain-cells = <0x0>;
195 #power-domain-cells = <0x0>;
200 #power-domain-cells = <0x0>;
205 #power-domain-cells = <0x0>;
210 #power-domain-cells = <0x0>;
215 #power-domain-cells = <0x0>;
220 #power-domain-cells = <0x0>;
225 #power-domain-cells = <0x0>;
230 #power-domain-cells = <0x0>;
235 #power-domain-cells = <0x0>;
240 #power-domain-cells = <0x0>;
245 #power-domain-cells = <0x0>;
246 pd-id = <0x3a 0x14 0x15>;
251 compatible = "arm,armv8-pmuv3";
252 interrupt-parent = <&gic>;
253 interrupts = <0 143 4>,
260 compatible = "arm,psci-0.2";
265 compatible = "xlnx,zynqmp-pm";
267 interrupt-parent = <&gic>;
268 interrupts = <0 35 4>;
272 compatible = "arm,armv8-timer";
273 interrupt-parent = <&gic>;
274 interrupts = <1 13 0xf08>,
281 compatible = "arm,cortex-a53-edac";
284 fpga_full: fpga-full {
285 compatible = "fpga-region";
287 #address-cells = <2>;
292 compatible = "xlnx,zynqmp-nvmem-fw";
293 #address-cells = <1>;
296 soc_revision: soc_revision@0 {
302 compatible = "xlnx,zynqmp-pcap-fpga";
305 rst: reset-controller {
306 compatible = "xlnx,zynqmp-reset";
310 xlnx_dp_snd_card: dp_snd_card {
311 compatible = "xlnx,dp-snd-card";
313 xlnx,dp-snd-pcm = <&xlnx_dp_snd_pcm0>, <&xlnx_dp_snd_pcm1>;
314 xlnx,dp-snd-codec = <&xlnx_dp_snd_codec0>;
317 xlnx_dp_snd_codec0: dp_snd_codec0 {
318 compatible = "xlnx,dp-snd-codec";
320 clock-names = "aud_clk";
323 xlnx_dp_snd_pcm0: dp_snd_pcm0 {
324 compatible = "xlnx,dp-snd-pcm";
326 dmas = <&xlnx_dpdma 4>;
330 xlnx_dp_snd_pcm1: dp_snd_pcm1 {
331 compatible = "xlnx,dp-snd-pcm";
333 dmas = <&xlnx_dpdma 5>;
337 xilinx_drm: xilinx_drm {
338 compatible = "xlnx,drm";
340 xlnx,encoder-slave = <&xlnx_dp>;
341 xlnx,connector-type = "DisplayPort";
342 xlnx,dp-sub = <&xlnx_dp_sub>;
344 xlnx,pixel-format = "rgb565";
346 dmas = <&xlnx_dpdma 3>;
350 dmas = <&xlnx_dpdma 0>,
353 dma-names = "dma0", "dma1", "dma2";
358 amba_apu: amba_apu@0 {
359 compatible = "simple-bus";
360 #address-cells = <2>;
362 ranges = <0 0 0 0 0xffffffff>;
364 gic: interrupt-controller@f9010000 {
365 compatible = "arm,gic-400", "arm,cortex-a15-gic";
366 #interrupt-cells = <3>;
367 reg = <0x0 0xf9010000 0x10000>,
368 <0x0 0xf9020000 0x20000>,
369 <0x0 0xf9040000 0x20000>,
370 <0x0 0xf9060000 0x20000>;
371 interrupt-controller;
372 interrupt-parent = <&gic>;
373 interrupts = <1 9 0xf04>;
378 compatible = "simple-bus";
380 #address-cells = <2>;
385 compatible = "xlnx,zynq-can-1.0";
387 clock-names = "can_clk", "pclk";
388 reg = <0x0 0xff060000 0x0 0x1000>;
389 interrupts = <0 23 4>;
390 interrupt-parent = <&gic>;
391 tx-fifo-depth = <0x40>;
392 rx-fifo-depth = <0x40>;
393 power-domains = <&pd_can0>;
397 compatible = "xlnx,zynq-can-1.0";
399 clock-names = "can_clk", "pclk";
400 reg = <0x0 0xff070000 0x0 0x1000>;
401 interrupts = <0 24 4>;
402 interrupt-parent = <&gic>;
403 tx-fifo-depth = <0x40>;
404 rx-fifo-depth = <0x40>;
405 power-domains = <&pd_can1>;
409 compatible = "arm,cci-400";
410 reg = <0x0 0xfd6e0000 0x0 0x9000>;
411 ranges = <0x0 0x0 0xfd6e0000 0x10000>;
412 #address-cells = <1>;
416 compatible = "arm,cci-400-pmu,r1";
417 reg = <0x9000 0x5000>;
418 interrupt-parent = <&gic>;
419 interrupts = <0 123 4>,
428 fpd_dma_chan1: dma@fd500000 {
430 compatible = "xlnx,zynqmp-dma-1.0";
431 reg = <0x0 0xfd500000 0x0 0x1000>;
432 interrupt-parent = <&gic>;
433 interrupts = <0 124 4>;
434 clock-names = "clk_main", "clk_apb";
435 xlnx,bus-width = <128>;
436 #stream-id-cells = <1>;
437 iommus = <&smmu 0x14e8>;
438 power-domains = <&pd_gdma>;
441 fpd_dma_chan2: dma@fd510000 {
443 compatible = "xlnx,zynqmp-dma-1.0";
444 reg = <0x0 0xfd510000 0x0 0x1000>;
445 interrupt-parent = <&gic>;
446 interrupts = <0 125 4>;
447 clock-names = "clk_main", "clk_apb";
448 xlnx,bus-width = <128>;
449 #stream-id-cells = <1>;
450 iommus = <&smmu 0x14e9>;
451 power-domains = <&pd_gdma>;
454 fpd_dma_chan3: dma@fd520000 {
456 compatible = "xlnx,zynqmp-dma-1.0";
457 reg = <0x0 0xfd520000 0x0 0x1000>;
458 interrupt-parent = <&gic>;
459 interrupts = <0 126 4>;
460 clock-names = "clk_main", "clk_apb";
461 xlnx,bus-width = <128>;
462 #stream-id-cells = <1>;
463 iommus = <&smmu 0x14ea>;
464 power-domains = <&pd_gdma>;
467 fpd_dma_chan4: dma@fd530000 {
469 compatible = "xlnx,zynqmp-dma-1.0";
470 reg = <0x0 0xfd530000 0x0 0x1000>;
471 interrupt-parent = <&gic>;
472 interrupts = <0 127 4>;
473 clock-names = "clk_main", "clk_apb";
474 xlnx,bus-width = <128>;
475 #stream-id-cells = <1>;
476 iommus = <&smmu 0x14eb>;
477 power-domains = <&pd_gdma>;
480 fpd_dma_chan5: dma@fd540000 {
482 compatible = "xlnx,zynqmp-dma-1.0";
483 reg = <0x0 0xfd540000 0x0 0x1000>;
484 interrupt-parent = <&gic>;
485 interrupts = <0 128 4>;
486 clock-names = "clk_main", "clk_apb";
487 xlnx,bus-width = <128>;
488 #stream-id-cells = <1>;
489 iommus = <&smmu 0x14ec>;
490 power-domains = <&pd_gdma>;
493 fpd_dma_chan6: dma@fd550000 {
495 compatible = "xlnx,zynqmp-dma-1.0";
496 reg = <0x0 0xfd550000 0x0 0x1000>;
497 interrupt-parent = <&gic>;
498 interrupts = <0 129 4>;
499 clock-names = "clk_main", "clk_apb";
500 xlnx,bus-width = <128>;
501 #stream-id-cells = <1>;
502 iommus = <&smmu 0x14ed>;
503 power-domains = <&pd_gdma>;
506 fpd_dma_chan7: dma@fd560000 {
508 compatible = "xlnx,zynqmp-dma-1.0";
509 reg = <0x0 0xfd560000 0x0 0x1000>;
510 interrupt-parent = <&gic>;
511 interrupts = <0 130 4>;
512 clock-names = "clk_main", "clk_apb";
513 xlnx,bus-width = <128>;
514 #stream-id-cells = <1>;
515 iommus = <&smmu 0x14ee>;
516 power-domains = <&pd_gdma>;
519 fpd_dma_chan8: dma@fd570000 {
521 compatible = "xlnx,zynqmp-dma-1.0";
522 reg = <0x0 0xfd570000 0x0 0x1000>;
523 interrupt-parent = <&gic>;
524 interrupts = <0 131 4>;
525 clock-names = "clk_main", "clk_apb";
526 xlnx,bus-width = <128>;
527 #stream-id-cells = <1>;
528 iommus = <&smmu 0x14ef>;
529 power-domains = <&pd_gdma>;
534 compatible = "arm,mali-400", "arm,mali-utgard";
535 reg = <0x0 0xfd4b0000 0x0 0x10000>;
536 interrupt-parent = <&gic>;
537 interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>;
538 interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1";
539 clock-names = "gpu", "gpu_pp0", "gpu_pp1";
540 power-domains = <&pd_gpu>;
543 /* LPDDMA default allows only secured access. inorder to enable
544 * These dma channels, Users should ensure that these dma
545 * Channels are allowed for non secure access.
547 lpd_dma_chan1: dma@ffa80000 {
549 compatible = "xlnx,zynqmp-dma-1.0";
550 reg = <0x0 0xffa80000 0x0 0x1000>;
551 interrupt-parent = <&gic>;
552 interrupts = <0 77 4>;
553 clock-names = "clk_main", "clk_apb";
554 xlnx,bus-width = <64>;
555 #stream-id-cells = <1>;
556 iommus = <&smmu 0x868>;
557 power-domains = <&pd_adma>;
560 lpd_dma_chan2: dma@ffa90000 {
562 compatible = "xlnx,zynqmp-dma-1.0";
563 reg = <0x0 0xffa90000 0x0 0x1000>;
564 interrupt-parent = <&gic>;
565 interrupts = <0 78 4>;
566 clock-names = "clk_main", "clk_apb";
567 xlnx,bus-width = <64>;
568 #stream-id-cells = <1>;
569 iommus = <&smmu 0x869>;
570 power-domains = <&pd_adma>;
573 lpd_dma_chan3: dma@ffaa0000 {
575 compatible = "xlnx,zynqmp-dma-1.0";
576 reg = <0x0 0xffaa0000 0x0 0x1000>;
577 interrupt-parent = <&gic>;
578 interrupts = <0 79 4>;
579 clock-names = "clk_main", "clk_apb";
580 xlnx,bus-width = <64>;
581 #stream-id-cells = <1>;
582 iommus = <&smmu 0x86a>;
583 power-domains = <&pd_adma>;
586 lpd_dma_chan4: dma@ffab0000 {
588 compatible = "xlnx,zynqmp-dma-1.0";
589 reg = <0x0 0xffab0000 0x0 0x1000>;
590 interrupt-parent = <&gic>;
591 interrupts = <0 80 4>;
592 clock-names = "clk_main", "clk_apb";
593 xlnx,bus-width = <64>;
594 #stream-id-cells = <1>;
595 iommus = <&smmu 0x86b>;
596 power-domains = <&pd_adma>;
599 lpd_dma_chan5: dma@ffac0000 {
601 compatible = "xlnx,zynqmp-dma-1.0";
602 reg = <0x0 0xffac0000 0x0 0x1000>;
603 interrupt-parent = <&gic>;
604 interrupts = <0 81 4>;
605 clock-names = "clk_main", "clk_apb";
606 xlnx,bus-width = <64>;
607 #stream-id-cells = <1>;
608 iommus = <&smmu 0x86c>;
609 power-domains = <&pd_adma>;
612 lpd_dma_chan6: dma@ffad0000 {
614 compatible = "xlnx,zynqmp-dma-1.0";
615 reg = <0x0 0xffad0000 0x0 0x1000>;
616 interrupt-parent = <&gic>;
617 interrupts = <0 82 4>;
618 clock-names = "clk_main", "clk_apb";
619 xlnx,bus-width = <64>;
620 #stream-id-cells = <1>;
621 iommus = <&smmu 0x86d>;
622 power-domains = <&pd_adma>;
625 lpd_dma_chan7: dma@ffae0000 {
627 compatible = "xlnx,zynqmp-dma-1.0";
628 reg = <0x0 0xffae0000 0x0 0x1000>;
629 interrupt-parent = <&gic>;
630 interrupts = <0 83 4>;
631 clock-names = "clk_main", "clk_apb";
632 xlnx,bus-width = <64>;
633 #stream-id-cells = <1>;
634 iommus = <&smmu 0x86e>;
635 power-domains = <&pd_adma>;
638 lpd_dma_chan8: dma@ffaf0000 {
640 compatible = "xlnx,zynqmp-dma-1.0";
641 reg = <0x0 0xffaf0000 0x0 0x1000>;
642 interrupt-parent = <&gic>;
643 interrupts = <0 84 4>;
644 clock-names = "clk_main", "clk_apb";
645 xlnx,bus-width = <64>;
646 #stream-id-cells = <1>;
647 iommus = <&smmu 0x86f>;
648 power-domains = <&pd_adma>;
651 mc: memory-controller@fd070000 {
652 compatible = "xlnx,zynqmp-ddrc-2.40a";
653 reg = <0x0 0xfd070000 0x0 0x30000>;
654 interrupt-parent = <&gic>;
655 interrupts = <0 112 4>;
658 nand0: nand@ff100000 {
659 compatible = "arasan,nfc-v3p10";
661 reg = <0x0 0xff100000 0x0 0x1000>;
662 clock-names = "clk_sys", "clk_flash";
663 interrupt-parent = <&gic>;
664 interrupts = <0 14 4>;
665 #address-cells = <2>;
667 #stream-id-cells = <1>;
668 iommus = <&smmu 0x872>;
669 power-domains = <&pd_nand>;
672 gem0: ethernet@ff0b0000 {
673 compatible = "cdns,zynqmp-gem";
675 interrupt-parent = <&gic>;
676 interrupts = <0 57 4>, <0 57 4>;
677 reg = <0x0 0xff0b0000 0x0 0x1000>;
678 clock-names = "pclk", "hclk", "tx_clk";
679 #address-cells = <1>;
681 #stream-id-cells = <1>;
682 iommus = <&smmu 0x874>;
683 power-domains = <&pd_eth0>;
686 gem1: ethernet@ff0c0000 {
687 compatible = "cdns,zynqmp-gem";
689 interrupt-parent = <&gic>;
690 interrupts = <0 59 4>, <0 59 4>;
691 reg = <0x0 0xff0c0000 0x0 0x1000>;
692 clock-names = "pclk", "hclk", "tx_clk";
693 #address-cells = <1>;
695 #stream-id-cells = <1>;
696 iommus = <&smmu 0x875>;
697 power-domains = <&pd_eth1>;
700 gem2: ethernet@ff0d0000 {
701 compatible = "cdns,zynqmp-gem";
703 interrupt-parent = <&gic>;
704 interrupts = <0 61 4>, <0 61 4>;
705 reg = <0x0 0xff0d0000 0x0 0x1000>;
706 clock-names = "pclk", "hclk", "tx_clk";
707 #address-cells = <1>;
709 #stream-id-cells = <1>;
710 iommus = <&smmu 0x876>;
711 power-domains = <&pd_eth2>;
714 gem3: ethernet@ff0e0000 {
715 compatible = "cdns,zynqmp-gem";
717 interrupt-parent = <&gic>;
718 interrupts = <0 63 4>, <0 63 4>;
719 reg = <0x0 0xff0e0000 0x0 0x1000>;
720 clock-names = "pclk", "hclk", "tx_clk";
721 #address-cells = <1>;
723 #stream-id-cells = <1>;
724 iommus = <&smmu 0x877>;
725 power-domains = <&pd_eth3>;
728 gpio: gpio@ff0a0000 {
729 compatible = "xlnx,zynqmp-gpio-1.0";
732 interrupt-parent = <&gic>;
733 interrupts = <0 16 4>;
734 interrupt-controller;
735 #interrupt-cells = <2>;
736 reg = <0x0 0xff0a0000 0x0 0x1000>;
738 power-domains = <&pd_gpio>;
742 compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10";
744 interrupt-parent = <&gic>;
745 interrupts = <0 17 4>;
746 reg = <0x0 0xff020000 0x0 0x1000>;
747 #address-cells = <1>;
749 power-domains = <&pd_i2c0>;
753 compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10";
755 interrupt-parent = <&gic>;
756 interrupts = <0 18 4>;
757 reg = <0x0 0xff030000 0x0 0x1000>;
758 #address-cells = <1>;
760 power-domains = <&pd_i2c1>;
763 ocm: memory-controller@ff960000 {
764 compatible = "xlnx,zynqmp-ocmc-1.0";
765 reg = <0x0 0xff960000 0x0 0x1000>;
766 interrupt-parent = <&gic>;
767 interrupts = <0 10 4>;
770 pcie: pcie@fd0e0000 {
771 compatible = "xlnx,nwl-pcie-2.11";
773 #address-cells = <3>;
775 #interrupt-cells = <1>;
778 interrupt-parent = <&gic>;
779 interrupts = <0 118 4>,
782 <0 115 4>, /* MSI_1 [63...32] */
783 <0 114 4>; /* MSI_0 [31...0] */
784 interrupt-names = "misc", "dummy", "intx",
786 msi-parent = <&pcie>;
787 reg = <0x0 0xfd0e0000 0x0 0x1000>,
788 <0x0 0xfd480000 0x0 0x1000>,
789 <0x80 0x00000000 0x0 0x1000000>;
790 reg-names = "breg", "pcireg", "cfg";
791 ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000 /* non-prefetchable memory */
792 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */
793 bus-range = <0x00 0xff>;
794 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
795 interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
796 <0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
797 <0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
798 <0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
799 power-domains = <&pd_pcie>;
800 pcie_intc: legacy-interrupt-controller {
801 interrupt-controller;
802 #address-cells = <0>;
803 #interrupt-cells = <1>;
809 compatible = "xlnx,zynqmp-qspi-1.0";
811 clock-names = "ref_clk", "pclk";
812 interrupts = <0 15 4>;
813 interrupt-parent = <&gic>;
815 reg = <0x0 0xff0f0000 0x0 0x1000>,
816 <0x0 0xc0000000 0x0 0x8000000>;
817 #address-cells = <1>;
819 #stream-id-cells = <1>;
820 iommus = <&smmu 0x873>;
821 power-domains = <&pd_qspi>;
825 compatible = "xlnx,zynqmp-rtc";
827 reg = <0x0 0xffa60000 0x0 0x100>;
828 interrupt-parent = <&gic>;
829 interrupts = <0 26 4>, <0 27 4>;
830 interrupt-names = "alarm", "sec";
831 calibration = <0x8000>;
834 serdes: zynqmp_phy@fd400000 {
835 compatible = "xlnx,zynqmp-psgtr";
837 reg = <0x0 0xfd400000 0x0 0x40000>,
838 <0x0 0xfd3d0000 0x0 0x1000>,
839 <0x0 0xff5e0000 0x0 0x1000>;
840 reg-names = "serdes", "siou", "lpd";
841 nvmem-cells = <&soc_revision>;
842 nvmem-cell-names = "soc_revision";
843 resets = <&rst 16>, <&rst 59>, <&rst 60>,
844 <&rst 61>, <&rst 62>, <&rst 63>,
845 <&rst 64>, <&rst 3>, <&rst 29>,
846 <&rst 30>, <&rst 31>, <&rst 32>;
847 reset-names = "sata_rst", "usb0_crst", "usb1_crst",
848 "usb0_hibrst", "usb1_hibrst", "usb0_apbrst",
849 "usb1_apbrst", "dp_rst", "gem0_rst",
850 "gem1_rst", "gem2_rst", "gem3_rst";
865 sata: ahci@fd0c0000 {
866 compatible = "ceva,ahci-1v84";
868 reg = <0x0 0xfd0c0000 0x0 0x2000>;
869 interrupt-parent = <&gic>;
870 interrupts = <0 133 4>;
871 power-domains = <&pd_sata>;
872 #stream-id-cells = <4>;
873 iommus = <&smmu 0x4c0>, <&smmu 0x4c1>,
874 <&smmu 0x4c2>, <&smmu 0x4c3>;
878 sdhci0: sdhci@ff160000 {
880 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
882 interrupt-parent = <&gic>;
883 interrupts = <0 48 4>;
884 reg = <0x0 0xff160000 0x0 0x1000>;
885 clock-names = "clk_xin", "clk_ahb";
886 xlnx,device_id = <0>;
887 #stream-id-cells = <1>;
888 iommus = <&smmu 0x870>;
889 power-domains = <&pd_sd0>;
890 nvmem-cells = <&soc_revision>;
891 nvmem-cell-names = "soc_revision";
894 sdhci1: sdhci@ff170000 {
896 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
898 interrupt-parent = <&gic>;
899 interrupts = <0 49 4>;
900 reg = <0x0 0xff170000 0x0 0x1000>;
901 clock-names = "clk_xin", "clk_ahb";
902 xlnx,device_id = <1>;
903 #stream-id-cells = <1>;
904 iommus = <&smmu 0x871>;
905 power-domains = <&pd_sd1>;
906 nvmem-cells = <&soc_revision>;
907 nvmem-cell-names = "soc_revision";
910 pinctrl0: pinctrl@ff180000 {
911 compatible = "xlnx,pinctrl-zynqmp";
913 reg = <0x0 0xff180000 0x0 0x1000>;
916 smmu: smmu@fd800000 {
917 compatible = "arm,mmu-500";
918 reg = <0x0 0xfd800000 0x0 0x20000>;
921 #global-interrupts = <1>;
922 interrupt-parent = <&gic>;
923 interrupts = <0 155 4>,
924 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
925 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
926 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
927 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>;
931 compatible = "cdns,spi-r1p6";
933 interrupt-parent = <&gic>;
934 interrupts = <0 19 4>;
935 reg = <0x0 0xff040000 0x0 0x1000>;
936 clock-names = "ref_clk", "pclk";
937 #address-cells = <1>;
939 power-domains = <&pd_spi0>;
943 compatible = "cdns,spi-r1p6";
945 interrupt-parent = <&gic>;
946 interrupts = <0 20 4>;
947 reg = <0x0 0xff050000 0x0 0x1000>;
948 clock-names = "ref_clk", "pclk";
949 #address-cells = <1>;
951 power-domains = <&pd_spi1>;
954 ttc0: timer@ff110000 {
955 compatible = "cdns,ttc";
957 interrupt-parent = <&gic>;
958 interrupts = <0 36 4>, <0 37 4>, <0 38 4>;
959 reg = <0x0 0xff110000 0x0 0x1000>;
961 power-domains = <&pd_ttc0>;
964 ttc1: timer@ff120000 {
965 compatible = "cdns,ttc";
967 interrupt-parent = <&gic>;
968 interrupts = <0 39 4>, <0 40 4>, <0 41 4>;
969 reg = <0x0 0xff120000 0x0 0x1000>;
971 power-domains = <&pd_ttc1>;
974 ttc2: timer@ff130000 {
975 compatible = "cdns,ttc";
977 interrupt-parent = <&gic>;
978 interrupts = <0 42 4>, <0 43 4>, <0 44 4>;
979 reg = <0x0 0xff130000 0x0 0x1000>;
981 power-domains = <&pd_ttc2>;
984 ttc3: timer@ff140000 {
985 compatible = "cdns,ttc";
987 interrupt-parent = <&gic>;
988 interrupts = <0 45 4>, <0 46 4>, <0 47 4>;
989 reg = <0x0 0xff140000 0x0 0x1000>;
991 power-domains = <&pd_ttc3>;
994 uart0: serial@ff000000 {
996 compatible = "cdns,uart-r1p12", "xlnx,xuartps";
998 interrupt-parent = <&gic>;
999 interrupts = <0 21 4>;
1000 reg = <0x0 0xff000000 0x0 0x1000>;
1001 clock-names = "uart_clk", "pclk";
1002 power-domains = <&pd_uart0>;
1005 uart1: serial@ff010000 {
1006 u-boot,dm-pre-reloc;
1007 compatible = "cdns,uart-r1p12", "xlnx,xuartps";
1008 status = "disabled";
1009 interrupt-parent = <&gic>;
1010 interrupts = <0 22 4>;
1011 reg = <0x0 0xff010000 0x0 0x1000>;
1012 clock-names = "uart_clk", "pclk";
1013 power-domains = <&pd_uart1>;
1016 usb0: usb0@ff9d0000 {
1017 #address-cells = <2>;
1019 status = "disabled";
1020 compatible = "xlnx,zynqmp-dwc3";
1021 reg = <0x0 0xff9d0000 0x0 0x100>;
1022 clock-names = "bus_clk", "ref_clk";
1023 power-domains = <&pd_usb0>;
1025 nvmem-cells = <&soc_revision>;
1026 nvmem-cell-names = "soc_revision";
1028 dwc3_0: dwc3@fe200000 {
1029 compatible = "snps,dwc3";
1030 status = "disabled";
1031 reg = <0x0 0xfe200000 0x0 0x40000>;
1032 interrupt-parent = <&gic>;
1033 interrupts = <0 65 4>, <0 69 4>;
1034 #stream-id-cells = <1>;
1035 iommus = <&smmu 0x860>;
1036 snps,quirk-frame-length-adjustment = <0x20>;
1042 usb1: usb1@ff9e0000 {
1043 #address-cells = <2>;
1045 status = "disabled";
1046 compatible = "xlnx,zynqmp-dwc3";
1047 reg = <0x0 0xff9e0000 0x0 0x100>;
1048 clock-names = "bus_clk", "ref_clk";
1049 power-domains = <&pd_usb1>;
1051 nvmem-cells = <&soc_revision>;
1052 nvmem-cell-names = "soc_revision";
1054 dwc3_1: dwc3@fe300000 {
1055 compatible = "snps,dwc3";
1056 status = "disabled";
1057 reg = <0x0 0xfe300000 0x0 0x40000>;
1058 interrupt-parent = <&gic>;
1059 interrupts = <0 70 4>, <0 74 4>;
1060 #stream-id-cells = <1>;
1061 iommus = <&smmu 0x861>;
1062 snps,quirk-frame-length-adjustment = <0x20>;
1068 watchdog0: watchdog@fd4d0000 {
1069 compatible = "cdns,wdt-r1p2";
1070 status = "disabled";
1071 interrupt-parent = <&gic>;
1072 interrupts = <0 113 1>;
1073 reg = <0x0 0xfd4d0000 0x0 0x1000>;
1077 xilinx_ams: ams@ffa50000 {
1078 compatible = "xlnx,zynqmp-ams";
1079 status = "disabled";
1080 interrupt-parent = <&gic>;
1081 interrupts = <0 56 4>;
1082 interrupt-names = "ams-irq";
1083 reg = <0x0 0xffa50000 0x0 0x800>;
1084 reg-names = "ams-base";
1085 #address-cells = <2>;
1087 #io-channel-cells = <1>;
1090 ams_ps: ams_ps@ffa50800 {
1091 compatible = "xlnx,zynqmp-ams-ps";
1092 status = "disabled";
1093 reg = <0x0 0xffa50800 0x0 0x400>;
1096 ams_pl: ams_pl@ffa50c00 {
1097 compatible = "xlnx,zynqmp-ams-pl";
1098 status = "disabled";
1099 reg = <0x0 0xffa50c00 0x0 0x400>;
1103 xlnx_dp: dp@fd4a0000 {
1104 compatible = "xlnx,v-dp";
1105 status = "disabled";
1106 reg = <0x0 0xfd4a0000 0x0 0x1000>;
1107 interrupts = <0 119 4>;
1108 interrupt-parent = <&gic>;
1109 clock-names = "aclk", "aud_clk";
1110 power-domains = <&pd_dp>;
1111 xlnx,dp-version = "v1.2";
1112 xlnx,max-lanes = <2>;
1113 xlnx,max-link-rate = <540000>;
1114 xlnx,max-bpc = <16>;
1116 xlnx,colormetry = "rgb";
1118 xlnx,audio-chan = <2>;
1119 xlnx,dp-sub = <&xlnx_dp_sub>;
1120 xlnx,max-pclock-frequency = <300000>;
1123 xlnx_dp_sub: dp_sub@fd4aa000 {
1124 compatible = "xlnx,dp-sub";
1125 status = "disabled";
1126 reg = <0x0 0xfd4aa000 0x0 0x1000>,
1127 <0x0 0xfd4ab000 0x0 0x1000>,
1128 <0x0 0xfd4ac000 0x0 0x1000>;
1129 reg-names = "blend", "av_buf", "aud";
1130 xlnx,output-fmt = "rgb";
1131 xlnx,vid-fmt = "yuyv";
1132 xlnx,gfx-fmt = "rgb565";
1133 power-domains = <&pd_dp>;
1136 xlnx_dpdma: dma@fd4c0000 {
1137 compatible = "xlnx,dpdma";
1138 status = "disabled";
1139 reg = <0x0 0xfd4c0000 0x0 0x1000>;
1140 interrupts = <0 122 4>;
1141 interrupt-parent = <&gic>;
1142 clock-names = "axi_clk";
1143 power-domains = <&pd_dp>;
1147 compatible = "xlnx,video0";
1150 compatible = "xlnx,video1";
1153 compatible = "xlnx,video2";
1155 dma-graphicschannel {
1156 compatible = "xlnx,graphics";
1159 compatible = "xlnx,audio0";
1162 compatible = "xlnx,audio1";