2 * dts file for Xilinx ZynqMP
4 * (C) Copyright 2014 - 2015, Xilinx, Inc.
6 * Michal Simek <michal.simek@xilinx.com>
8 * SPDX-License-Identifier: GPL-2.0+
12 compatible = "xlnx,zynqmp";
21 compatible = "arm,cortex-a53", "arm,armv8";
23 enable-method = "psci";
24 operating-points-v2 = <&cpu_opp_table>;
26 cpu-idle-states = <&CPU_SLEEP_0>;
30 compatible = "arm,cortex-a53", "arm,armv8";
32 enable-method = "psci";
34 operating-points-v2 = <&cpu_opp_table>;
35 cpu-idle-states = <&CPU_SLEEP_0>;
39 compatible = "arm,cortex-a53", "arm,armv8";
41 enable-method = "psci";
43 operating-points-v2 = <&cpu_opp_table>;
44 cpu-idle-states = <&CPU_SLEEP_0>;
48 compatible = "arm,cortex-a53", "arm,armv8";
50 enable-method = "psci";
52 operating-points-v2 = <&cpu_opp_table>;
53 cpu-idle-states = <&CPU_SLEEP_0>;
57 entry-method = "arm,psci";
59 CPU_SLEEP_0: cpu-sleep-0 {
60 compatible = "arm,idle-state";
61 arm,psci-suspend-param = <0x40000000>;
63 entry-latency-us = <300>;
64 exit-latency-us = <600>;
65 min-residency-us = <10000>;
70 cpu_opp_table: cpu_opp_table {
71 compatible = "operating-points-v2";
74 opp-hz = /bits/ 64 <1199999988>;
75 opp-microvolt = <1000000>;
76 clock-latency-ns = <500000>;
79 opp-hz = /bits/ 64 <599999994>;
80 opp-microvolt = <1000000>;
81 clock-latency-ns = <500000>;
84 opp-hz = /bits/ 64 <399999996>;
85 opp-microvolt = <1000000>;
86 clock-latency-ns = <500000>;
89 opp-hz = /bits/ 64 <299999997>;
90 opp-microvolt = <1000000>;
91 clock-latency-ns = <500000>;
96 compatible = "arm,dcc";
102 compatible = "xlnx,zynqmp-genpd";
105 #power-domain-cells = <0x0>;
110 #power-domain-cells = <0x0>;
115 #power-domain-cells = <0x0>;
120 #power-domain-cells = <0x0>;
125 #power-domain-cells = <0x0>;
130 #power-domain-cells = <0x0>;
135 #power-domain-cells = <0x0>;
140 #power-domain-cells = <0x0>;
145 #power-domain-cells = <0x0>;
150 #power-domain-cells = <0x0>;
155 #power-domain-cells = <0x0>;
160 #power-domain-cells = <0x0>;
165 #power-domain-cells = <0x0>;
170 /* fixme: what to attach to */
171 #power-domain-cells = <0x0>;
176 #power-domain-cells = <0x0>;
181 #power-domain-cells = <0x0>;
186 #power-domain-cells = <0x0>;
191 #power-domain-cells = <0x0>;
196 #power-domain-cells = <0x0>;
201 #power-domain-cells = <0x0>;
206 #power-domain-cells = <0x0>;
211 #power-domain-cells = <0x0>;
216 #power-domain-cells = <0x0>;
221 #power-domain-cells = <0x0>;
226 #power-domain-cells = <0x0>;
231 #power-domain-cells = <0x0>;
236 #power-domain-cells = <0x0>;
241 #power-domain-cells = <0x0>;
246 #power-domain-cells = <0x0>;
247 pd-id = <0x3a 0x14 0x15>;
252 compatible = "arm,armv8-pmuv3";
253 interrupt-parent = <&gic>;
254 interrupts = <0 143 4>,
261 compatible = "arm,psci-0.2";
266 compatible = "xlnx,zynqmp-pm";
268 interrupt-parent = <&gic>;
269 interrupts = <0 35 4>;
273 compatible = "arm,armv8-timer";
274 interrupt-parent = <&gic>;
275 interrupts = <1 13 0xf01>,
282 compatible = "arm,cortex-a53-edac";
286 compatible = "xlnx,zynqmp-pcap-fpga";
289 amba_apu: amba_apu@0 {
290 compatible = "simple-bus";
291 #address-cells = <2>;
293 ranges = <0 0 0 0 0xffffffff>;
295 gic: interrupt-controller@f9010000 {
296 compatible = "arm,gic-400", "arm,cortex-a15-gic";
297 #interrupt-cells = <3>;
298 reg = <0x0 0xf9010000 0x10000>,
299 <0x0 0xf9020000 0x20000>,
300 <0x0 0xf9040000 0x20000>,
301 <0x0 0xf9060000 0x20000>;
302 interrupt-controller;
303 interrupt-parent = <&gic>;
304 interrupts = <1 9 0xf04>;
309 compatible = "simple-bus";
311 #address-cells = <2>;
316 compatible = "xlnx,zynq-can-1.0";
318 clock-names = "can_clk", "pclk";
319 reg = <0x0 0xff060000 0x0 0x1000>;
320 interrupts = <0 23 4>;
321 interrupt-parent = <&gic>;
322 tx-fifo-depth = <0x40>;
323 rx-fifo-depth = <0x40>;
324 power-domains = <&pd_can0>;
328 compatible = "xlnx,zynq-can-1.0";
330 clock-names = "can_clk", "pclk";
331 reg = <0x0 0xff070000 0x0 0x1000>;
332 interrupts = <0 24 4>;
333 interrupt-parent = <&gic>;
334 tx-fifo-depth = <0x40>;
335 rx-fifo-depth = <0x40>;
336 power-domains = <&pd_can1>;
340 compatible = "arm,cci-400";
341 reg = <0x0 0xfd6e0000 0x0 0x9000>;
342 ranges = <0x0 0x0 0xfd6e0000 0x10000>;
343 #address-cells = <1>;
347 compatible = "arm,cci-400-pmu,r1";
348 reg = <0x9000 0x5000>;
349 interrupt-parent = <&gic>;
350 interrupts = <0 123 4>,
359 fpd_dma_chan1: dma@fd500000 {
361 compatible = "xlnx,zynqmp-dma-1.0";
362 reg = <0x0 0xfd500000 0x0 0x1000>;
363 interrupt-parent = <&gic>;
364 interrupts = <0 124 4>;
365 clock-names = "clk_main", "clk_apb";
366 xlnx,bus-width = <128>;
367 #stream-id-cells = <1>;
368 iommus = <&smmu 0x14e8>;
369 power-domains = <&pd_gdma>;
372 fpd_dma_chan2: dma@fd510000 {
374 compatible = "xlnx,zynqmp-dma-1.0";
375 reg = <0x0 0xfd510000 0x0 0x1000>;
376 interrupt-parent = <&gic>;
377 interrupts = <0 125 4>;
378 clock-names = "clk_main", "clk_apb";
379 xlnx,bus-width = <128>;
380 #stream-id-cells = <1>;
381 iommus = <&smmu 0x14e9>;
382 power-domains = <&pd_gdma>;
385 fpd_dma_chan3: dma@fd520000 {
387 compatible = "xlnx,zynqmp-dma-1.0";
388 reg = <0x0 0xfd520000 0x0 0x1000>;
389 interrupt-parent = <&gic>;
390 interrupts = <0 126 4>;
391 clock-names = "clk_main", "clk_apb";
392 xlnx,bus-width = <128>;
393 #stream-id-cells = <1>;
394 iommus = <&smmu 0x14ea>;
395 power-domains = <&pd_gdma>;
398 fpd_dma_chan4: dma@fd530000 {
400 compatible = "xlnx,zynqmp-dma-1.0";
401 reg = <0x0 0xfd530000 0x0 0x1000>;
402 interrupt-parent = <&gic>;
403 interrupts = <0 127 4>;
404 clock-names = "clk_main", "clk_apb";
405 xlnx,bus-width = <128>;
406 #stream-id-cells = <1>;
407 iommus = <&smmu 0x14eb>;
408 power-domains = <&pd_gdma>;
411 fpd_dma_chan5: dma@fd540000 {
413 compatible = "xlnx,zynqmp-dma-1.0";
414 reg = <0x0 0xfd540000 0x0 0x1000>;
415 interrupt-parent = <&gic>;
416 interrupts = <0 128 4>;
417 clock-names = "clk_main", "clk_apb";
418 xlnx,bus-width = <128>;
419 #stream-id-cells = <1>;
420 iommus = <&smmu 0x14ec>;
421 power-domains = <&pd_gdma>;
424 fpd_dma_chan6: dma@fd550000 {
426 compatible = "xlnx,zynqmp-dma-1.0";
427 reg = <0x0 0xfd550000 0x0 0x1000>;
428 interrupt-parent = <&gic>;
429 interrupts = <0 129 4>;
430 clock-names = "clk_main", "clk_apb";
431 xlnx,bus-width = <128>;
432 #stream-id-cells = <1>;
433 iommus = <&smmu 0x14ed>;
434 power-domains = <&pd_gdma>;
437 fpd_dma_chan7: dma@fd560000 {
439 compatible = "xlnx,zynqmp-dma-1.0";
440 reg = <0x0 0xfd560000 0x0 0x1000>;
441 interrupt-parent = <&gic>;
442 interrupts = <0 130 4>;
443 clock-names = "clk_main", "clk_apb";
444 xlnx,bus-width = <128>;
445 #stream-id-cells = <1>;
446 iommus = <&smmu 0x14ee>;
447 power-domains = <&pd_gdma>;
450 fpd_dma_chan8: dma@fd570000 {
452 compatible = "xlnx,zynqmp-dma-1.0";
453 reg = <0x0 0xfd570000 0x0 0x1000>;
454 interrupt-parent = <&gic>;
455 interrupts = <0 131 4>;
456 clock-names = "clk_main", "clk_apb";
457 xlnx,bus-width = <128>;
458 #stream-id-cells = <1>;
459 iommus = <&smmu 0x14ef>;
460 power-domains = <&pd_gdma>;
465 compatible = "arm,mali-400", "arm,mali-utgard";
466 reg = <0x0 0xfd4b0000 0x0 0x30000>;
467 interrupt-parent = <&gic>;
468 interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>;
469 interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1";
470 power-domains = <&pd_gpu>;
473 /* LPDDMA default allows only secured access. inorder to enable
474 * These dma channels, Users should ensure that these dma
475 * Channels are allowed for non secure access.
477 lpd_dma_chan1: dma@ffa80000 {
479 compatible = "xlnx,zynqmp-dma-1.0";
480 clock-names = "clk_main", "clk_apb";
481 reg = <0x0 0xffa80000 0x0 0x1000>;
482 interrupt-parent = <&gic>;
483 interrupts = <0 77 4>;
484 xlnx,bus-width = <64>;
485 #stream-id-cells = <1>;
486 iommus = <&smmu 0x868>;
487 power-domains = <&pd_adma>;
490 lpd_dma_chan2: dma@ffa90000 {
492 compatible = "xlnx,zynqmp-dma-1.0";
493 clock-names = "clk_main", "clk_apb";
494 reg = <0x0 0xffa90000 0x0 0x1000>;
495 interrupt-parent = <&gic>;
496 interrupts = <0 78 4>;
497 xlnx,bus-width = <64>;
498 #stream-id-cells = <1>;
499 iommus = <&smmu 0x869>;
500 power-domains = <&pd_adma>;
503 lpd_dma_chan3: dma@ffaa0000 {
505 compatible = "xlnx,zynqmp-dma-1.0";
506 clock-names = "clk_main", "clk_apb";
507 reg = <0x0 0xffaa0000 0x0 0x1000>;
508 interrupt-parent = <&gic>;
509 interrupts = <0 79 4>;
510 xlnx,bus-width = <64>;
511 #stream-id-cells = <1>;
512 iommus = <&smmu 0x86a>;
513 power-domains = <&pd_adma>;
516 lpd_dma_chan4: dma@ffab0000 {
518 compatible = "xlnx,zynqmp-dma-1.0";
519 clock-names = "clk_main", "clk_apb";
520 reg = <0x0 0xffab0000 0x0 0x1000>;
521 interrupt-parent = <&gic>;
522 interrupts = <0 80 4>;
523 xlnx,bus-width = <64>;
524 #stream-id-cells = <1>;
525 iommus = <&smmu 0x86b>;
526 power-domains = <&pd_adma>;
529 lpd_dma_chan5: dma@ffac0000 {
531 compatible = "xlnx,zynqmp-dma-1.0";
532 clock-names = "clk_main", "clk_apb";
533 reg = <0x0 0xffac0000 0x0 0x1000>;
534 interrupt-parent = <&gic>;
535 interrupts = <0 81 4>;
536 xlnx,bus-width = <64>;
537 #stream-id-cells = <1>;
538 iommus = <&smmu 0x86c>;
539 power-domains = <&pd_adma>;
542 lpd_dma_chan6: dma@ffad0000 {
544 compatible = "xlnx,zynqmp-dma-1.0";
545 clock-names = "clk_main", "clk_apb";
546 reg = <0x0 0xffad0000 0x0 0x1000>;
547 interrupt-parent = <&gic>;
548 interrupts = <0 82 4>;
549 xlnx,bus-width = <64>;
550 #stream-id-cells = <1>;
551 iommus = <&smmu 0x86d>;
552 power-domains = <&pd_adma>;
555 lpd_dma_chan7: dma@ffae0000 {
557 compatible = "xlnx,zynqmp-dma-1.0";
558 clock-names = "clk_main", "clk_apb";
559 reg = <0x0 0xffae0000 0x0 0x1000>;
560 interrupt-parent = <&gic>;
561 interrupts = <0 83 4>;
562 xlnx,bus-width = <64>;
563 #stream-id-cells = <1>;
564 iommus = <&smmu 0x86e>;
565 power-domains = <&pd_adma>;
568 lpd_dma_chan8: dma@ffaf0000 {
570 compatible = "xlnx,zynqmp-dma-1.0";
571 clock-names = "clk_main", "clk_apb";
572 reg = <0x0 0xffaf0000 0x0 0x1000>;
573 interrupt-parent = <&gic>;
574 interrupts = <0 84 4>;
575 xlnx,bus-width = <64>;
576 #stream-id-cells = <1>;
577 iommus = <&smmu 0x86f>;
578 power-domains = <&pd_adma>;
581 mc: memory-controller@fd070000 {
582 compatible = "xlnx,zynqmp-ddrc-2.40a";
583 reg = <0x0 0xfd070000 0x0 0x30000>;
584 interrupt-parent = <&gic>;
585 interrupts = <0 112 4>;
588 nand0: nand@ff100000 {
589 compatible = "arasan,nfc-v3p10";
591 reg = <0x0 0xff100000 0x0 0x1000>;
592 clock-names = "clk_sys", "clk_flash";
593 interrupt-parent = <&gic>;
594 interrupts = <0 14 4>;
595 #address-cells = <2>;
597 #stream-id-cells = <1>;
598 iommus = <&smmu 0x872>;
599 power-domains = <&pd_nand>;
602 gem0: ethernet@ff0b0000 {
603 compatible = "cdns,zynqmp-gem";
605 interrupt-parent = <&gic>;
606 interrupts = <0 57 4>, <0 57 4>;
607 reg = <0x0 0xff0b0000 0x0 0x1000>;
608 clock-names = "pclk", "hclk", "tx_clk";
609 #address-cells = <1>;
611 #stream-id-cells = <1>;
612 iommus = <&smmu 0x874>;
613 power-domains = <&pd_eth0>;
616 gem1: ethernet@ff0c0000 {
617 compatible = "cdns,zynqmp-gem";
619 interrupt-parent = <&gic>;
620 interrupts = <0 59 4>, <0 59 4>;
621 reg = <0x0 0xff0c0000 0x0 0x1000>;
622 clock-names = "pclk", "hclk", "tx_clk";
623 #address-cells = <1>;
625 #stream-id-cells = <1>;
626 iommus = <&smmu 0x875>;
627 power-domains = <&pd_eth1>;
630 gem2: ethernet@ff0d0000 {
631 compatible = "cdns,zynqmp-gem";
633 interrupt-parent = <&gic>;
634 interrupts = <0 61 4>, <0 61 4>;
635 reg = <0x0 0xff0d0000 0x0 0x1000>;
636 clock-names = "pclk", "hclk", "tx_clk";
637 #address-cells = <1>;
639 #stream-id-cells = <1>;
640 iommus = <&smmu 0x876>;
641 power-domains = <&pd_eth2>;
644 gem3: ethernet@ff0e0000 {
645 compatible = "cdns,zynqmp-gem";
647 interrupt-parent = <&gic>;
648 interrupts = <0 63 4>, <0 63 4>;
649 reg = <0x0 0xff0e0000 0x0 0x1000>;
650 clock-names = "pclk", "hclk", "tx_clk";
651 #address-cells = <1>;
653 #stream-id-cells = <1>;
654 iommus = <&smmu 0x877>;
655 power-domains = <&pd_eth3>;
658 gpio: gpio@ff0a0000 {
659 compatible = "xlnx,zynqmp-gpio-1.0";
662 interrupt-parent = <&gic>;
663 interrupts = <0 16 4>;
664 interrupt-controller;
665 #interrupt-cells = <2>;
666 reg = <0x0 0xff0a0000 0x0 0x1000>;
667 power-domains = <&pd_gpio>;
671 compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10";
673 interrupt-parent = <&gic>;
674 interrupts = <0 17 4>;
675 reg = <0x0 0xff020000 0x0 0x1000>;
676 #address-cells = <1>;
678 power-domains = <&pd_i2c0>;
682 compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10";
684 interrupt-parent = <&gic>;
685 interrupts = <0 18 4>;
686 reg = <0x0 0xff030000 0x0 0x1000>;
687 #address-cells = <1>;
689 power-domains = <&pd_i2c1>;
692 ocm: memory-controller@ff960000 {
693 compatible = "xlnx,zynqmp-ocmc-1.0";
694 reg = <0x0 0xff960000 0x0 0x1000>;
695 interrupt-parent = <&gic>;
696 interrupts = <0 10 4>;
699 pcie: pcie@fd0e0000 {
700 compatible = "xlnx,nwl-pcie-2.11";
702 #address-cells = <3>;
704 #interrupt-cells = <1>;
707 interrupt-parent = <&gic>;
708 interrupts = <0 118 4>,
711 <0 115 4>, /* MSI_1 [63...32] */
712 <0 114 4>; /* MSI_0 [31...0] */
713 interrupt-names = "misc","dummy","intx", "msi1", "msi0";
714 msi-parent = <&pcie>;
715 reg = <0x0 0xfd0e0000 0x0 0x1000>,
716 <0x0 0xfd480000 0x0 0x1000>,
717 <0x80 0x00000000 0x0 0x1000000>;
718 reg-names = "breg", "pcireg", "cfg";
719 ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000 /* non-prefetchable memory */
720 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */
721 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
722 interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
723 <0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
724 <0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
725 <0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
726 power-domains = <&pd_pcie>;
727 pcie_intc: legacy-interrupt-controller {
728 interrupt-controller;
729 #address-cells = <0>;
730 #interrupt-cells = <1>;
735 compatible = "xlnx,zynqmp-qspi-1.0";
737 clock-names = "ref_clk", "pclk";
738 interrupts = <0 15 4>;
739 interrupt-parent = <&gic>;
741 reg = <0x0 0xff0f0000 0x0 0x1000>,
742 <0x0 0xc0000000 0x0 0x8000000>;
743 #address-cells = <1>;
745 #stream-id-cells = <1>;
746 iommus = <&smmu 0x873>;
747 power-domains = <&pd_qspi>;
751 compatible = "xlnx,zynqmp-rtc";
753 reg = <0x0 0xffa60000 0x0 0x100>;
754 interrupt-parent = <&gic>;
755 interrupts = <0 26 4>, <0 27 4>;
756 interrupt-names = "alarm", "sec";
759 serdes: zynqmp_phy@fd400000 {
760 compatible = "xlnx,zynqmp-psgtr";
762 reg = <0x0 0xfd400000 0x0 0x40000>,
763 <0x0 0xfd3d0000 0x0 0x1000>,
764 <0x0 0xfd1a0000 0x0 0x1000>,
765 <0x0 0xff5e0000 0x0 0x1000>;
766 reg-names = "serdes", "siou", "fpd", "lpd";
767 xlnx,tx_termination_fix;
782 sata: ahci@fd0c0000 {
783 compatible = "ceva,ahci-1v84";
785 reg = <0x0 0xfd0c0000 0x0 0x2000>;
786 interrupt-parent = <&gic>;
787 interrupts = <0 133 4>;
788 power-domains = <&pd_sata>;
791 sdhci0: sdhci@ff160000 {
793 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
795 interrupt-parent = <&gic>;
796 interrupts = <0 48 4>;
797 reg = <0x0 0xff160000 0x0 0x1000>;
798 clock-names = "clk_xin", "clk_ahb";
799 xlnx,device_id = <0>;
800 #stream-id-cells = <1>;
801 iommus = <&smmu 0x870>;
802 power-domains = <&pd_sd0>;
805 sdhci1: sdhci@ff170000 {
807 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
809 interrupt-parent = <&gic>;
810 interrupts = <0 49 4>;
811 reg = <0x0 0xff170000 0x0 0x1000>;
812 clock-names = "clk_xin", "clk_ahb";
813 xlnx,device_id = <1>;
814 #stream-id-cells = <1>;
815 iommus = <&smmu 0x871>;
816 power-domains = <&pd_sd1>;
819 smmu: smmu@fd800000 {
820 compatible = "arm,mmu-500";
821 reg = <0x0 0xfd800000 0x0 0x20000>;
823 #global-interrupts = <1>;
824 interrupt-parent = <&gic>;
825 interrupts = <0 155 4>,
826 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
827 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
828 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
829 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>;
830 mmu-masters = < &gem0 0x874
845 &fpd_dma_chan1 0x14e8
846 &fpd_dma_chan2 0x14e9
847 &fpd_dma_chan3 0x14ea
848 &fpd_dma_chan4 0x14eb
849 &fpd_dma_chan5 0x14ec
850 &fpd_dma_chan6 0x14ed
851 &fpd_dma_chan7 0x14ee
852 &fpd_dma_chan8 0x14ef
859 compatible = "cdns,spi-r1p6";
861 interrupt-parent = <&gic>;
862 interrupts = <0 19 4>;
863 reg = <0x0 0xff040000 0x0 0x1000>;
864 clock-names = "ref_clk", "pclk";
865 #address-cells = <1>;
867 power-domains = <&pd_spi0>;
871 compatible = "cdns,spi-r1p6";
873 interrupt-parent = <&gic>;
874 interrupts = <0 20 4>;
875 reg = <0x0 0xff050000 0x0 0x1000>;
876 clock-names = "ref_clk", "pclk";
877 #address-cells = <1>;
879 power-domains = <&pd_spi1>;
882 ttc0: timer@ff110000 {
883 compatible = "cdns,ttc";
885 interrupt-parent = <&gic>;
886 interrupts = <0 36 4>, <0 37 4>, <0 38 4>;
887 reg = <0x0 0xff110000 0x0 0x1000>;
889 power-domains = <&pd_ttc0>;
892 ttc1: timer@ff120000 {
893 compatible = "cdns,ttc";
895 interrupt-parent = <&gic>;
896 interrupts = <0 39 4>, <0 40 4>, <0 41 4>;
897 reg = <0x0 0xff120000 0x0 0x1000>;
899 power-domains = <&pd_ttc1>;
902 ttc2: timer@ff130000 {
903 compatible = "cdns,ttc";
905 interrupt-parent = <&gic>;
906 interrupts = <0 42 4>, <0 43 4>, <0 44 4>;
907 reg = <0x0 0xff130000 0x0 0x1000>;
909 power-domains = <&pd_ttc2>;
912 ttc3: timer@ff140000 {
913 compatible = "cdns,ttc";
915 interrupt-parent = <&gic>;
916 interrupts = <0 45 4>, <0 46 4>, <0 47 4>;
917 reg = <0x0 0xff140000 0x0 0x1000>;
919 power-domains = <&pd_ttc3>;
922 uart0: serial@ff000000 {
924 compatible = "cdns,uart-r1p12", "xlnx,xuartps";
926 interrupt-parent = <&gic>;
927 interrupts = <0 21 4>;
928 reg = <0x0 0xff000000 0x0 0x1000>;
929 clock-names = "uart_clk", "pclk";
930 power-domains = <&pd_uart0>;
933 uart1: serial@ff010000 {
935 compatible = "cdns,uart-r1p12", "xlnx,xuartps";
937 interrupt-parent = <&gic>;
938 interrupts = <0 22 4>;
939 reg = <0x0 0xff010000 0x0 0x1000>;
940 clock-names = "uart_clk", "pclk";
941 power-domains = <&pd_uart1>;
945 #address-cells = <2>;
948 compatible = "xlnx,zynqmp-dwc3";
949 clock-names = "bus_clk", "ref_clk";
950 clocks = <&clk125>, <&clk125>;
951 #stream-id-cells = <1>;
952 iommus = <&smmu 0x860>;
953 power-domains = <&pd_usb0>;
956 dwc3_0: dwc3@fe200000 {
957 compatible = "snps,dwc3";
959 reg = <0x0 0xfe200000 0x0 0x40000>;
960 interrupt-parent = <&gic>;
961 interrupts = <0 65 4>;
962 /* snps,quirk-frame-length-adjustment = <0x20>; */
968 #address-cells = <2>;
971 compatible = "xlnx,zynqmp-dwc3";
972 clock-names = "bus_clk", "ref_clk";
973 clocks = <&clk125>, <&clk125>;
974 #stream-id-cells = <1>;
975 iommus = <&smmu 0x861>;
976 power-domains = <&pd_usb1>;
979 dwc3_1: dwc3@fe300000 {
980 compatible = "snps,dwc3";
982 reg = <0x0 0xfe300000 0x0 0x40000>;
983 interrupt-parent = <&gic>;
984 interrupts = <0 70 4>;
985 /* snps,quirk-frame-length-adjustment = <0x20>; */
990 watchdog0: watchdog@fd4d0000 {
991 compatible = "cdns,wdt-r1p2";
993 interrupt-parent = <&gic>;
994 interrupts = <0 113 1>;
995 reg = <0x0 0xfd4d0000 0x0 0x1000>;
999 xilinx_drm: xilinx_drm {
1000 compatible = "xlnx,drm";
1001 status = "disabled";
1002 xlnx,encoder-slave = <&xlnx_dp>;
1003 xlnx,connector-type = "DisplayPort";
1004 xlnx,dp-sub = <&xlnx_dp_sub>;
1006 xlnx,pixel-format = "rgb565";
1008 dmas = <&xlnx_dpdma 3>;
1012 dmas = <&xlnx_dpdma 0>,
1015 dma-names = "dma0", "dma1", "dma2";
1020 xlnx_dp: dp@fd4a0000 {
1021 compatible = "xlnx,v-dp";
1022 status = "disabled";
1023 reg = <0x0 0xfd4a0000 0x0 0x1000>;
1024 interrupts = <0 119 4>;
1025 interrupt-parent = <&gic>;
1026 clock-names = "aclk", "aud_clk";
1027 xlnx,dp-version = "v1.2";
1028 xlnx,max-lanes = <2>;
1029 xlnx,max-link-rate = <540000>;
1030 xlnx,max-bpc = <16>;
1032 xlnx,colormetry = "rgb";
1034 xlnx,audio-chan = <2>;
1035 xlnx,dp-sub = <&xlnx_dp_sub>;
1036 xlnx,max-pclock-frequency = <300000>;
1039 xlnx_dp_snd_card: dp_snd_card {
1040 compatible = "xlnx,dp-snd-card";
1041 status = "disabled";
1042 xlnx,dp-snd-pcm = <&xlnx_dp_snd_pcm0>, <&xlnx_dp_snd_pcm1>;
1043 xlnx,dp-snd-codec = <&xlnx_dp_snd_codec0>;
1046 xlnx_dp_snd_codec0: dp_snd_codec0 {
1047 compatible = "xlnx,dp-snd-codec";
1048 status = "disabled";
1049 clock-names = "aud_clk";
1052 xlnx_dp_snd_pcm0: dp_snd_pcm0 {
1053 compatible = "xlnx,dp-snd-pcm";
1054 status = "disabled";
1055 dmas = <&xlnx_dpdma 4>;
1059 xlnx_dp_snd_pcm1: dp_snd_pcm1 {
1060 compatible = "xlnx,dp-snd-pcm";
1061 status = "disabled";
1062 dmas = <&xlnx_dpdma 5>;
1066 xlnx_dp_sub: dp_sub@fd4aa000 {
1067 compatible = "xlnx,dp-sub";
1068 status = "disabled";
1069 reg = <0x0 0xfd4aa000 0x0 0x1000>,
1070 <0x0 0xfd4ab000 0x0 0x1000>,
1071 <0x0 0xfd4ac000 0x0 0x1000>;
1072 reg-names = "blend", "av_buf", "aud";
1073 xlnx,output-fmt = "rgb";
1074 xlnx,vid-fmt = "yuyv";
1075 xlnx,gfx-fmt = "rgb565";
1078 xlnx_dpdma: dma@fd4c0000 {
1079 compatible = "xlnx,dpdma";
1080 status = "disabled";
1081 reg = <0x0 0xfd4c0000 0x0 0x1000>;
1082 interrupts = <0 122 4>;
1083 interrupt-parent = <&gic>;
1084 clock-names = "axi_clk";
1088 compatible = "xlnx,video0";
1091 compatible = "xlnx,video1";
1094 compatible = "xlnx,video2";
1096 dma-graphicschannel {
1097 compatible = "xlnx,graphics";
1100 compatible = "xlnx,audio0";
1103 compatible = "xlnx,audio1";